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參數(shù)資料
| 型號： | TMX320C6201 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors(1600MIPS at 200MHz，8個功能單元并行操作的DSP) |
| 中文描述： | 數(shù)字信號處理器（1600MIPS在200MHz，8個功能單元并行操作的數(shù)字信號處理器） |
| 文件頁數(shù)： | 55/72頁 |
| 文件大?。?/td> | 1552K |
| 代理商： | TMX320C6201 |
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TMX320C6201
DIGITAL SIGNAL PROCESSOR
SPRS051B – JANUARY 1997 – REVISED JUNE 1997
55
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
synchronous DRAM (SDRAM) cycles
The SDRAM cycles on the ‘C6201 device are limited to non-burst operation for the initial version of the
’320C6201. Both read and write cycles consist of three commands sent sequentially to the SDRAM device (see
Figure 36 and Figure 37). Each of the commands is encoded by ’320C6201 by a different mix of signal levels
on CE, SDA10, SDRAS, SDCAS, and SDWE control lines. First, the ACTV command activates one of two
SDRAM internal banks. The READ or WRITE commands transfer data between the ’320C6201 device and the
SDRAM memory. Finally, the DCAB command deactivates both banks of the SDRAM (banks A and B). The
SDRAM uses the CLKOUT2 clock to transfer data and to latch commands. In a read cycle, the data is driven
on the bus by the SDRAM exactly two CLKOUT2 cycles following the rising edge of SDCAS. The ’320C6201
DSP programs read latency into the SDRAM at the time of SDRAM initialization.
The BE control signals behave differently during SDRAM cycles than they do for other types of memory. Each
BE signal must be connected to the corresponding SDRAM DQM input. For reads, the DQM controls become
output-enables and for the writes they assume a function of write masking (associated with burst operation of
SDRAM).
Figure 38 shows the initialization commands sent to the SDRAM following reset. First, both banks of the
SDRAM are deactivated with the DCAB command. Next, eight refresh cycles are issued, followed by the mode
register set (MRS) command that initializes control registers inside the SDRAM in accordance with the values
stored in the EMIF SDRAM control register. During the MRS command, the SDRAM initialization data is actually
output on the address bus instead of on the data bus.
The SDRAM device must be refreshed periodically. Since one of the address pins, EA10, is involved in the
refresh operation, it has been duplicated for the exclusive use of the SDRAM interface to avoid interfering with
other memory cycles that can be active during refresh. Figure 39 shows an SDRAM-refresh cycle in the middle
of an asynchronous-SRAM-read sequence. Two commands are used in a single refresh cycle. The first one
deactivates both SDRAM banks (DCAB) and the second one performs a CAS-before-RAS refresh. It is evident
in the figure that despite the use of address lead EA10 by the DCAB command, the asynchronous memory read
cycles are progressing uninterrupted due to the duplicate SDA10 pin.
timing requirements for synchronous DRAM (SDRAM) cycles
NO
MIN
MAX
UNIT
5
tsu(D-CKH)
th(CKH-D)
Setup time, read ED before CLKOUT1 high
0.5
ns
6
Hold time, read ED valid after CLKOUT1 high
2.0
ns
switching characteristics for synchronous DRAM (SDRAM) cycles
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1
td(CKH-CE)
td(CKH-D)
td(CKH-SDA10)
td(CKH-SDRAS)
Delay time, CLKOUT1 high to CE valid
1.7
ns
3
4
8
Delay time, CLKOUT1 high to EA valid
2.0
1.1
ns
Delay time, CLKOUT1 high to ED valid
Delay time, CLKOUT1 high to SDRAS valid
ns
1.5
7
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Delay time, CLKOUT1 high to SDA10 valid
ns
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