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參數(shù)資料
| 型號(hào)： | TMX320C6201 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Digital Signal Processors(1600MIPS at 200MHz，8個(gè)功能單元并行操作的DSP) |
| 中文描述： | 數(shù)字信號(hào)處理器（1600MIPS在200MHz，8個(gè)功能單元并行操作的數(shù)字信號(hào)處理器） |
| 文件頁數(shù)： | 31/72頁 |
| 文件大小： | 1552K |
| 代理商： | TMX320C6201 |
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TMX320C6201
DIGITAL SIGNAL PROCESSOR
SPRS051B – JANUARY 1997 – REVISED JUNE 1997
31
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
clock characteristics and timing
The ‘320C6201 uses an external oscillator to drive the on-chip phase-locked loop (PLL) circuit that generates
all internal and external clocks. The PLL typically multiplies the external oscillator frequency by four or by two
and feeds the resulting clock to the CLKOUT1 output pin. The internal version of CLKOUT1 is used by the
processor as an instruction-cycle clock. Most timing parameters of this device are defined relative to the
CLKOUT1 clock and specifically to its rising edge. CLKOUT2 is another output clock derived from CLKOUT1
at half of its frequency. It clocks some synchronous memories such as SDRAM.
In addition to multiply-by-2 and multiply-by-4 mode, the clock circuit can operate in multiply-by-one mode, where
the input clock frequency is the same as the CLKOUT1 output-clock frequency (the PLL is bypassed). The
factors to consider in choosing the multiply factor include board-level noise and clock jitter. The by-four mode
minimizes board noise, and the by-two mode reduces the jitter. The clock mode is controlled by the two
CLKMODE pins as shown in Figure 16.
The amount of time that the PLL needs to synchronize to the output frequency depends on the CLKIN and
CLKOUT1 frequencies and is typically in the range of tens of microseconds. See Table 6 for the exact time. The
synchronization time affects the duration of the reset signal in that the reset has to be asserted long enough
for the PLL to synchronize to the proper output frequency when changing the PLL configuration or following
power up.
Three PLLFREQ pins identify the range of CLKOUT1 frequencies to which the PLL is expected to synchronize.
The PLL also requires two bypass capacitors (between PLLV and PLLG), external low-pass filter components
(R1, C1, C2) and an EMI filter (see Figure 16). The values for R1, C1, C2, and the filter depend on the CLKIN
and CLKOUT1 frequencies. See Table 6 to choose correct values for the PLL external components and the EMI
filter.
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