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參數(shù)資料
| 型號： | TMX320C6201 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors(1600MIPS at 200MHz，8個功能單元并行操作的DSP) |
| 中文描述： | 數(shù)字信號處理器（1600MIPS在200MHz，8個功能單元并行操作的數(shù)字信號處理器） |
| 文件頁數(shù)： | 35/72頁 |
| 文件大?。?/td> | 1552K |
| 代理商： | TMX320C6201 |
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TMX320C6201
DIGITAL SIGNAL PROCESSOR
SPRS051B – JANUARY 1997 – REVISED JUNE 1997
35
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
power-down modes (idle1, 2 and 3) (continued)
The power-down modes are triggered by setting bits 0–2 in the PWRD field of the control status register (CSR).
Idle3 mode can be aborted only by device reset, while idle1 and idle2 modes also can be terminated by an
enabled interrupt or any interrupt (enabled or not), as directed by bits 3 and 4 of the PWRD field. When writing
to CSR, all bits of the PWRD field should be set at the same time. When more then one logic 1 is written to the
PRWD field bits 0–2, the highest order enabled bit determines the power-down mode.
Table 7. Characteristics of the Power-Down Modes (idle1, 2, and 3)
POWER-DOWN
MODE
TRIGGER ACTION
WAKE–UP METHOD
EFFECT ON CHIP’S OPERATION
Idle1
Write a logic 1 into bit 0 of PWRD field
of CSR register
Internal interrupt, external
interrupt, or reset
CPU halted (except for the interrupt logic)
Idle2
Write a logic 1 into bit 1 of PWRD field
of CSR register
External interrupt or reset
Peripherals halted and CPU halted (except for
the interrupt logic)
Idle3
Write a logic 1 into bit 2 of PWRD field
of CSR register
Reset only
PLL operation is halted, stopping the clock tree
from switching and resulting in the entire chip
being halted
The wake-up from idle2 or idle3 can be triggered by either an enabled interrupt, or any interrupt (enabled or not). The first case is selected by
writing a logic 1 into bit 3 of the CSR PWRD field, and the second case is selected by writing a logic 1 into bit 4 of the same field. When both
bits 3 and 4 are set to 1, any interrupt (enabled or not) wakes the processor from idle1 or idle2. If power-down mode is terminated by a non-enabled
interrupt, the program execution returns to the instruction following the one that caused the powerdown by setting the idle bits in the CSR.
Wake-up by an enabled interrupt executes the corresponding interrupt service routine first, prior to returning to the code aborted by the power
down.
thermal performance
Like most high-performance processors, the ’320C6201 can dissipate some thermal energy during normal
operation. The high level of integration, high clock frequency, and large on-chip memory arrays have an
increased effect on the silicon-junction temperature (T
J
) compared with a lower performance DSP. To ensure
proper operation and device reliability, the silicon-junction temperature must not exceed the maximum
temperature (related to maximum case temperature T
CMAX
). Under operating conditions, system-level thermal
management is needed to assist with dissipating the heat away from the chip package. A passive heat sink
provides a reliable and cost-effective method for removing the excess heat. The size and shape of the heat sink
depend on the operating conditions of the ’320C6201 device and the characteristics of the system within which
it operates.
’320C6201 device operating conditions that can affect power dissipation:
–
Operating frequency
–
Chip manufacturing process type
–
Use of power-down (idle) modes
–
Amount of on-chip activity:
Number of functional units exercised every cycle
Frequency of internal data memory accesses
Frequency of internal program memory accesses
Rate at which the internal buses are charged and discharged
Activity level of on-chip peripherals (DMAs, serial ports, and others)
Rate at which data is driven off and on the chip
System considerations for choosing a heat sink:
–
Air-flow rate over the board housing the ’320C6201
–
Ambient-air temperature
–
Area/type of joint between package and heat sink
–
Board design and layout
P
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