參數(shù)資料
型號(hào)： TMX320C6201
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors(1600MIPS at 200MHz，8個(gè)功能單元并行操作的DSP)
中文描述： 數(shù)字信號(hào)處理器（1600MIPS在200MHz，8個(gè)功能單元并行操作的數(shù)字信號(hào)處理器）
文件頁數(shù)： 24/72頁
文件大?。?/td> 1552K
代理商： TMX320C6201
TMX320C6201
DIGITAL SIGNAL PROCESSOR
SPRS051B – JANUARY 1997 – REVISED JUNE 1997
24
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
memory mapped registers – DMA
31
26
25
24
23
19
18
14
13
8
7
6
5
4
3
2
1
0
DMA
Control
Register
RSV
TCINIT
RSV
WSYNC
RSYNC
RSV
DST_DIR
SRC_DIR
STATUS
START
(see
Note A)
Enables
interrupt
generation
following
transfer
Identifies
interrupt
synchronizing
the writes (or
no sync)
Identifies
interrupt
synchronizing
the reads (or
no sync)
Increment
or
decrement
destination
address
after each
transfer
Increment
or
decrement
source
address
after each
transfer
Shows if
DMA is
started or
stopped
Starts,
pauses,
aborts
DMA
operation
31
30
25
24
2
1
0
DMA
Source
Address
Register
SA
RSV
SRC_ADR
RSV
Source addr select:
internal-data memory or
external-data memory
/internal-program memory
These bits are 0 to cover
EMIF and internal program
memory spaces
Source-Word Address
These bits are 0 since DMA
supports only word-sized
transfers
31
30
25
24
2
1
0
DMA
Destination
Address
Register
SA
RSV
SRC_ADR
RSV
Destination addr select:
internal data memory or
external data memory /internal
program memory
These bits are 0 to cover
EMIF and internal program
memory spaces
Destination Word Address
These bits are 0 since DMA
only supports word-sized
transfers
31
16
15
0
DMA-
Transfer
Counter
Register
RSV
TC
Reserved
DMA Transfer Counter (see Note B)
NOTES: A. Only 0s are permitted to be written to reserved fields of the registers.
B. The transfer counter is decremented upon the completion of the write portion of each transfer.
Figure 8. DMA Memory-Mapped Registers
P
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMX320C6201BGJC31 制造商:Rochester Electronics LLC 功能描述:320C6201B 352PIN GJC REV3.1 35MM - Bulk
TMX320C6201BGJL31 制造商:Texas Instruments 功能描述:
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