SPNS110E – AUGUST 2005 – REVISED MAY 2008 ........................................" />
參數(shù)資料
型號(hào)： TMS470R1A384PZ-T
廠商： Texas Instruments
文件頁(yè)數(shù)： 8/62頁(yè)
文件大?。?/td> 0K
描述： IC RISC MCU 384K FLASH 100-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： TMS470
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 48MHz
連通性： CAN，C2Slb，I²C，SCI，SPI
外圍設(shè)備： DMA，PWM，WDT
輸入/輸出數(shù)： 53
程序存儲(chǔ)器容量： 384KB（384K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.71 V ~ 2.05 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12x10b
振蕩器型： 外部
工作溫度： -40°C ~ 105°C
封裝/外殼： 100-LQFP
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 718 (CN2011-ZH PDF)
配用： 296-23003-ND - KIT DEV KICKSTART TMS470
其它名稱(chēng)： 296-19292
Memory Selects
SPNS110E – AUGUST 2005 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com
Memory selects allow the user to address memory arrays (i.e., flash, RAM, and HET RAM) at user-defined
addresses. Each memory select has its own set (low and high) of memory base address registers (MFBAHRx
and MFBALRx) that, together, define the array's starting (base) address, block size, and protection.
The base address of each memory select is configurable to any memory address boundary that is a multiple of
the decoded block size. For more information on how to control and configure these memory select registers, see
the bus structure and memory sections of the TMS470R1x System Module Reference Guide (literature number
SPNU189).
For the memory selection assignments and the memory selected, see Table 3.
Table 3. TMS470R1A384 Memory Selection Assignment
MEMORY
MEMORY SELECTED
MEMORY
STATIC MEM
MPU
MEMORY BASE ADDRESS REGISTER
SELECT
(ALL INTERNAL)
SIZE(1)
CTL REGISTER
0 (fine)
FLASH
NO
MFBAHR0 and MFBALR0
384K
1 (fine)
FLASH
NO
MFBAHR1 and MFBALR1
2 (fine)
RAM
YES
MFBAHR2 and MFBALR2
32K(2)
3 (fine)
RAM
YES
MFBAHR3 and MFBALR3
4 (fine)
HET RAM
1K
NO
MFBAHR4 and MFBALR4
SMCR1
4MB (x8)
5 (fine)
CS[5]/GIOC[3]
NO
MCBAHR2 and MCBALR2
SMCR5
1MB (x16)
4MB (x8)
6 (fine)
CS[6]/GIOC[4]
NO
MCBAHR3 and MCBALR3
SMCR6
1MB (x16)
(1)
x8 refers to size of memory in 8-bits; x16 refers to size of memory in 16-bits.
(2)
The starting addresses for both RAM memory-select signals cannot be offset from each other by a multiple of the user-defined block
size in the memory-base address register.
RAM
The A384 device contains 32K-bytes of internal static RAM configurable by the SYS module to be addressed
within the range of 0x0000_0000 to 0xFFE0_0000. This A384 RAM is implemented in one 32K-byte array
selected by two memory-select signals.
NOTE:
This A384 configuration imposes an additional constraint on the memory map for
RAM; the starting addresses for both RAM memory selects cannot be offset from
each other by the multiples of the size of the physical RAM (i.e., 32K bytes for the
A384 device). The A384 RAM is addressed through memory selects 2 and 3.
The RAM can be protected by the memory protection unit (MPU) portion of the SYS module, allowing the user
finer blocks of memory protection than is allowed by the memory selects. The MPU is ideal for protecting an
operating system while allowing access to the current task. For more detailed information on the MPU portion of
the SYS module and memory protection, see the memory section of the TMS470R1x System Module Reference
Guide (literature number SPNU189).
16
Copyright 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): TMS470R1A384
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