Vsrc Ri MibADC Input Pin
參數(shù)資料
型號: TMS470R1A384PZ-T
廠商: Texas Instruments
文件頁數(shù): 51/62頁
文件大?。?/td> 0K
描述: IC RISC MCU 384K FLASH 100-LQFP
標準包裝: 90
系列: TMS470
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 48MHz
連通性: CAN,C2Slb,I²C,SCI,SPI
外圍設(shè)備: DMA,PWM,WDT
輸入/輸出數(shù): 53
程序存儲器容量: 384KB(384K x 8)
程序存儲器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 2.05 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 100-LQFP
包裝: 托盤
產(chǎn)品目錄頁面: 718 (CN2011-ZH PDF)
配用: 296-23003-ND - KIT DEV KICKSTART TMS470
其它名稱: 296-19292
Parasitic
Capacitance
Vsrc
Ri
MibADC
Input Pin
Rs
Sample
Capacitor
Ci
Rleak
Sample Switch
External
Multi-Buffer ADC Timing Requirements
0
1
2
3
4
5
0 ... 101
0 ... 100
0 ... 011
0 ... 010
0 ... 001
0 ... 000
0 ... 110
Analog Input Value (LSB)
1 LSB
0
1
2
3
4
5
0 ... 101
0 ... 100
0 ... 011
0 ... 010
0 ... 001
0 ... 000
0 ... 110
1 LSB
Differential Linearity
Error(- 1/2 LSB)
Differential Linearity
Error(1/2 LSB)
www.ti.com ......................................................................................................................................................... SPNS110E – AUGUST 2005 – REVISED MAY 2008
Figure 23. MibADC Input Equivalent Circuit
MIN
NOM
MAX UNIT
tc(ADCLK)
Cycle time, MibADC clock
0.05
s
td(SH)
Delay time, sample and hold time
1
s
td(C)
Delay time, conversion time
0.55
s
td(SHC)
(1)
Delay time, total sample/hold and conversion time
1.55
s
(1)
This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors; for
more details, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).
The differential nonlinearity error shown in Figure 24 (sometimes referred to as differential linearity) is the
difference between an actual step width and the ideal value of 1 LSB.
A.
1 LSB = (ADREFHI - ADREFLO)/2
10
Figure 24. Differential Nonlinearity (DNL)
Copyright 2005–2008, Texas Instruments Incorporated
55
Product Folder Link(s): TMS470R1A384
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