SPNS110E – AUGUST 2005 – REVISED MAY 2008 ............................" />
參數(shù)資料
型號(hào)： TMS470R1A384PZ-T
廠商： Texas Instruments
文件頁數(shù)： 13/62頁
文件大小： 0K
描述： IC RISC MCU 384K FLASH 100-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： TMS470
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 48MHz
連通性： CAN，C2Slb，I²C，SCI，SPI
外圍設(shè)備： DMA，PWM，WDT
輸入/輸出數(shù)： 53
程序存儲(chǔ)器容量： 384KB（384K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.71 V ~ 2.05 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12x10b
振蕩器型： 外部
工作溫度： -40°C ~ 105°C
封裝/外殼： 100-LQFP
包裝： 托盤
產(chǎn)品目錄頁面： 718 (CN2011-ZH PDF)
配用： 296-23003-ND - KIT DEV KICKSTART TMS470
其它名稱： 296-19292
Direct Memory Access (DMA)
SPNS110E – AUGUST 2005 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com
The DMA controller transfers data to and from any specified location in the A384 memory map (except for
restricted memory locations like the system control registers area). The DMA manages up to 16 channels, and
supports data transfer for both on-chip and off-chip memories and peripherals. The DMA controller is connected
to both the CPU and peripheral buses, enabling these data transfers to occur in parallel with CPU activity and,
thus, maximizing overall system performance.
Although the DMA controller has two possible configurations for the A384 device, the DMA controller
configuration is 32 control packets and 16 channels.
For the A384 DMA request hardwired configuration, see Table 5.
Table 5. DMA Request Lines Connections(1)
MODULES
DMA REQUEST INTERRUPT SOURCES
DMA CHANNEL
EBM
Expansion bus DMA request
EBDMAREQ0
DMAREQ[0]
SPI1
SPI1 end-receive
SPI1DMA0
DMAREQ[1]
SPI1
SPI1 end-transmit
SPI1DMA1
DMAREQ[2]
I2C1
I2C1 read
I2C1DMA0
DMAREQ[3]
SCI1
SCI1 end-receive
SCI1DMA0
DMAREQ[4]
SCI1
SCI1 end-transmit
SCI1DMA1
DMAREQ[5]
I2C1
I2C1 write
I2C1DMA1
DMAREQ[6]
SPI2
SPI2 end-receive
SPI2DMA0
DMAREQ[7]
SPI2
SPI2 end-transmit
SPI2DMA1
DMAREQ[8]
I2C2/C2SIb
I2C2 read/C2SIb end-receive
I2C2DMA0/C2SIDMA0
DMAREQ[9]
I2C2/C2SIb
I2C2 write/C2SIb end-transmit
I2C2DMA1/C2SIDMA1
DMAREQ[10]
I2C3
I2C3 read
I2C3DMA0
DMAREQ[11]
I2C3
I2C3 write
I2C3DMA1
DMAREQ[12]
Reserved
DMAREQ[13]
SCI2/SPI3
SCI2 end-receive
SCI2DMA0
DMAREQ[14]
SCI2/SPI3
SCI2 end-transmit
SCI2DMA1
DMAREQ[15]
(1)
For DMA channels with more than one assigned request source (I2C2/C2SIb), only one of the sources listed can be the DMA request
generator in a given application. The device has software control to ensure that there are no conflicts between requesting modules.
Each channel has two control packets attached to it, allowing the DMA to continuously load RAM and generate
periodic interrupts so that the data can be read by the CPU. The control packets allow for the interrupt enable,
and the channels determine the priority level of the interrupt.
DMA transfers occur in one of two modes:
Non-request mode (used when transferring from memory to memory)
Request mode (used when transferring from memory to peripheral)
For more detailed functional information on the DMA controller, see the TMS470R1x Direct Memory Access
(DMA) Controller Reference Guide (literature number SPNU194).
20
Copyright 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): TMS470R1A384
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