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www.ti.com ......................................................................................................................................................... SPNS110E – AUGUST 2005 – REVISED MAY 2008
Table 2. Terminal Functions
TERMINAL
INTERNAL
INPUT
OUTPUT
PULLUP/
DESCRIPTION
VOLTAGE(1)(2)
CURRENT(3)
NAME
PZ
PGE
PULLDOWN
HIGH-END TIMER (HET)
HET[0]
51
73
Timer input capture or output compare. The
HET[1]
50
72
HET[8:0,18,20,22] applicable pins can be
HET[2]
49
71
programmed as general-purpose input/output
HET[3]
46
66
(GIO) pins. All are high-resolution pins.
The high-resolution (HR) SHARE feature allows
HET[4]
45
65
even HR pins to share the next higher odd HR
HET[5]
44
63
pin structures. This HR sharing is independent
3.3 V
2 mA
of whether or not the odd pin is available
HET[6]
6
9
externally. If an odd pin is available externally
HET[7]
7
11
and shared, then the odd pin can only be used
HET[8]
8
12
as a general-purpose I/O. For more information
on HR SHARE, see the TMS470R1x High-End
HET[18]
9
15
Timer (HET) Reference Guide (literature number
HET[20]
12
18
SPNU199).
HET[22]
13
19
STANDARD CAN CONTROLLER (SCC)
CAN1SRX
58
83
5-V tolerant
4 mA
SCC1 receive pin or GIO pin
CAN1STX
59
84
3.3 V
2 mA
SCC1 transmit pin or GIO pin
CAN2SRX
37
54
5-V tolerant
4 mA
SCC2 receive pin or GIO pin
CAN2STX
38
55
3.3 V
2 mA
SCC 2 transmit pin or GIO pin
CLASS II SERIAL INTERFACE (C2SIB)
C2SILPN
14
21
3.3 V
2 mA
C2SIb module loopback enable pin or GIO pin
C2SIRX
15
22
5-V tolerant
4 mA
C2SIb module receive data input pin or GIO pin
C2SIb module transmit data output pin or GIO
C2SITX
16
24
3.3 V
2 mA
pin
GENERAL-PURPOSE I/O (GIO)
GIOA[0]/INT[0]
99
141
GIOA[1]/INT[1]/ECLK
96
136
GIOA[2]/INT[2]
95
134
General-purpose input/output pins.
GIOA[7:0]/INT[7:0] are interrupt-capable pins.
GIOA[3]/INT[3]
94
133
5-V tolerant
4 mA
GIOA[1]/INT[1]/ECLK pin is multiplexed with the
GIOA[4]/INT[4]
89
127
external clock-out function of the external clock
prescale (ECP) module.
GIOA[5]/INT[5]
67
98
GIOA[6]/INT[6]
55
78
GIOA[7]/INT[7]
56
79
GIOB[0]/DMAREQ[0]
30
43
GIOC[0]/EBOE
-
135
GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:],
GIOC[1]/EBWR[0]
-
128
GIOF[7:0], GIOG[7:0], and GIOH[5:0] are
3.3 V
2 mA
IPD (20 A)
multiplexed with the expansion bus module.
GIOC[2]/EBWR[1]
-
126
GIOC[3]/EBCS[5]
-
120
GIOC[4]/EBCS[6]
-
119
(1)
PWR = power, GND = ground, REF = reference voltage, NC = no connect
(2)
All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
(3)
IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST
state.)
Copyright 2005–2008, Texas Instruments Incorporated
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