![](http://datasheet.mmic.net.cn/Texas-Instruments/TMS470R1A384PZQ_datasheet_99827/TMS470R1A384PZQ_19.png)
www.ti.com ......................................................................................................................................................... SPNS110E – AUGUST 2005 – REVISED MAY 2008
Table 4. A384 Peripherals, System Module, and Flash Base Addresses
ADDRESS RANGE
CONNECTING MODULE
PERIPHERAL SELECTS
BASE ADDRESS
ENDING ADDRESS
SYSTEM
0xFFFF_FFCC
0x FFFF_FFFF
N/A
Reserved
0xFFFF_FF60
0xFFFF_FFCB
N/A
PSA
0xFFFF_FF40
0xFFFF_FF5F
N/A
CIM
0xFFFF_FF20
0xFFFF_FF3F
N/A
RTI
0xFFFF_FF00
0xFFFF_FF1F
N/A
DMA
0xFFFF_FE80
0xFFFF_FEFF
N/A
DEC
0xFFFF_FE00
0xFFFF_FE7F
N/A
MMC
0xFFFF_FD00
0xFFFF_FD7F
N/A
IEM
0xFFFF_FC00
0xFFFF_FCFF
N/A
Reserved
0xFFFF_FB00
0xFFFF_FBFF
N/A
Reserved
0xFFFF_FA00
0xFFFF_FAFF
N/A
DMA CMD BUFFER
0xFFFF_F800
0xFFFF_F9FF
N/A
Reserved
0xFFF8_0000
0xFFFF_F7FF
N/A
HET
0xFFF7_FC00
0xFFF7_FFFF
PS[0]
SPI1
0xFFF7_F800
0xFFF7_FBFF
PS[1]
SCI2
0XFFF7_F500
0XFFF7_F7FF
PS[2]
SCI1
0xFFF7_F400
0xFFF7_F4FF
MibADC
0xFFF7_F000
0xFFF7_F3FF
PS[3]
ECP
0xFFF7_EF00
0xFFF7_EFFF
Reserved
0xFFF7_EE00
0xFFF7_EEFF
PS[4]
EBM
0xFFF7_ED00
0xFFF7_EDFF
GIO
0xFFF7_EC00
0xFFF7_ECFF
Reserved
0xFFF7_E400
0xFFF7_EBFF
PS[5]–PS[6]
Reserved
0xFFF7_E300
0xFFF7_E3FF
SCC2
0xFFF7_E200
0xFFF7_E2FF
PS[7]
Reserved
0xFFF7_E100
0xFFF7_E1FF
SCC1
0xFFF7_E000
0xFFF7_E0FF
Reserved
0xFFF7_DF00
0xFFF7_DFFF
SCC2 RAM
0xFFF7_DE00
0xFFF7_DEFF
PS[8]
Reserved
0xFFF7_DD00
0xFFF7_DDFF
SCC1 RAM
0xFFF7_DC00
0xFFF7_DCFF
Reserved
0xFFF7_DB00
0xFFF7_DBFF
I2C3
0xFFF7_DA00
0xFFF7_DAFF
PS[9]
I2C2
0xFFF7_D900
0xFFF7_D9FF
I2C1
0xFFF7_D800
0xFFF7_D8FF
SPI2
0xFFF7_D400
0xFFF7_D7FF
PS[10]
Reserved
0xFFF7_CC00
0xFFF7_D3FF
PS[11]–PS[12]
C2SIb
0xFFF7_C800
0xFFF7_CBFF
PS[13]
Reserved
0xFFF7_C000
0xFFF7_C7FF
PS[14]–PS[15]
Reserved
0xFFF0_0000
0xFFF7_BFFF
N/A
Flash Control Registers
0xFFE8_8000
0xFFE8_BFFF
N/A
MPU Control Registers
0xFFE8_4000
0xFFE8_4023
N/A
Copyright 2005–2008, Texas Instruments Incorporated
19