參數(shù)資料
型號(hào): TMS320LF2407APGEA
廠商: TEXAS INSTRUMENTS INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 16-BIT, 20 MHz, OTHER DSP, PQFP144
封裝: GREEN, PLASTIC, LQFP-144
文件頁數(shù): 45/134頁
文件大?。?/td> 1724K
代理商: TMS320LF2407APGEA
TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
18
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options (Continued)
PIN NAME
LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
ADDRESS, DATA, AND MEMORY CONTROL SIGNALS (CONTINUED)
READY
120
READY is pulled low to add wait states for external accesses.
READY indicates that an external device is prepared for a bus
transaction to be completed. If the device is not ready, it pulls the
READY pin low. The processor waits one cycle and checks
READY
again.
Note
that
the
processor
performs
READY-detection if at least one software wait state is
programmed. To meet the external READY timing parameters,
the wait-state generator control register (WSGR) should be
programmed for at least one wait state.
(
↑)
MP/MC
118
Microprocessor/Microcomputer mode select. If this pin is low
during reset, the device is put in microcomputer mode and
program execution begins at 0000h of internal program memory
(Flash EEPROM). A high value during reset puts the device in
microprocessor mode and program execution begins at 0000h
of external program memory. This line sets the MP/MC bit (bit 2
in the SCSR2 register).
(
↓)
ENA_144
122
Active high to enable external interface signals. If pulled low, the
2407A behaves like the 2406A/2403A/2402A—i.e., it has no
external memory and generates an illegal address if DS is
asserted. This pin has an internal pulldown.
(
↓)
VIS_OE
97
Visibility output enable (active when data bus is output). This pin
is active (low) whenever the external data bus is driving as an
output during visibility mode. Can be used by external decode
logic to prevent data bus contention while running in visibility
mode.
A0
80
Bit 0 of the 16-bit address bus
A1
78
Bit 1 of the 16-bit address bus
A2
74
Bit 2 of the 16-bit address bus
A3
71
Bit 3 of the 16-bit address bus
A4
68
Bit 4 of the 16-bit address bus
A5
64
Bit 5 of the 16-bit address bus
A6
61
Bit 6 of the 16-bit address bus
A7
57
Bit 7 of the 16-bit address bus
A8
53
Bit 8 of the 16-bit address bus
A9
51
Bit 9 of the 16-bit address bus
A10
48
Bit 10 of the 16-bit address bus
A11
45
Bit 11 of the 16-bit address bus
Bold, italicized pin names indicate pin function after reset.
GPIO General-purpose input/output pin. All GPIOs come up as input after reset.
§ It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
# No power supply pin (VDD, VDDO, VCCA, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for
proper device operation.
LEGEND:
↑ Internal pullup
↓ Internal pulldown
(Typical active pullup/pulldown value is
±16 A.)
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