參數(shù)資料
型號: TMS320LF2407APGEA
廠商: TEXAS INSTRUMENTS INC
元件分類: 數(shù)字信號處理
英文描述: 16-BIT, 20 MHz, OTHER DSP, PQFP144
封裝: GREEN, PLASTIC, LQFP-144
文件頁數(shù): 12/134頁
文件大小: 1724K
代理商: TMS320LF2407APGEA
TMS320LF2407A,TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145L JULY 2000 REVISED SEPTEMBER 2007
109
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
10-bit analog-to-digital converter (ADC) (continued)
internal ADC module timing (see Figure 52)
MIN
MAX
UNIT
tc(AD)
Cycle time, ADC prescaled clock
33.3
ns
tc(AD)
Cycle time, ADC prescaled clock
33.3
ns
Pulse duration, total sample/hold and
tw(SHC)
Pulse duration, total sample/hold and
conversion time
500
ns
tw(SHC)
conversion time
500
ns
td(SOC-SH)
Delay time, start of conversion to beginning of sample and hold
2tc(CO)
ns
tw(SH)
Pulse duration, sample and hold time
2tc(AD)§
32tc(AD)
ns
tw(C)
Pulse duration, total conversion time
10tc(AD)
ns
td(EOC)
Delay time, end of conversion to data loaded into result register
2tc(CO)
ns
td(ADCINT)
Delay time, ADC flag to ADC interrupt
2tc(CO)
ns
The ADC timing diagram represents a typical conversion sequence. See the ADC chapter in the TMS320LF/LC240xA DSP Controllers Reference
Guide: System and Peripherals (literature number SPRU357) for more details.
The total sample/hold and conversion time is determined by the summation of td(SOC-SH), tw(SH), tw(C), and td(EOC).
§ Can be varied by ACQ Prescaler bits in the ADCTRL1 register
0
3
2
4
51
tw(C)
6
7
8
tc(AD)
ADC Clock
Analog Input
Bit Converted
td(SOCSH)
EOC/Convert
Internal Start/
Sample Hold
Start of Convert
XFR to RESULTn
tw(SHC)
td(EOC)
9
tw(SH)
td(ADCINT)
ADC Interrupt
Figure 52. Analog-to-Digital Internal Module Timing
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相關(guān)代理商/技術(shù)參數(shù)
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