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參數(shù)資料
| 型號： | TMS320LC545 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors(20/25ns指令周期， 高性能，大并行度，特殊指令集可有效實現(xiàn)多種復雜算法及應用的DSP) |
| 中文描述： | 數(shù)字信號處理器（20/25ns指令周期，高性能，大并行度，特殊指令集可有效實現(xiàn)多種復雜算法及應用的數(shù)字信號處理器） |
| 文件頁數(shù)： | 37/107頁 |
| 文件大?。?/td> | 2149K |
| 代理商： | TMS320LC545 |
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TMS320C54x, TMS320LC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039A – FEBRUARY 1996 – REVISED JULY 1997
34
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
switching from DIV mode to PLL mode (continued)
Once the PLLNDIV bit is set, the PLLCOUNT timer begins being decremented from its preset value. When the
PLLCOUNT timer reaches zero, the switch to PLL mode takes effect after six CLKIN cycles plus 3.5 PLL cycles
(CLKOUT frequency). When the switch to PLL mode is completed, the PLLSTATUS bit in the CLKMD register
is read as 1. Note that during the PLL lockup period, the ’C54x continues operating in DIV mode.
The following software example shows an instruction that can be used to switch from DIV mode to PLL
with a CLKIN frequency of 13 MHz and PLLCOUNT = 41 (decimal).
3,
STM
#0010000101001111b, CLKMD
switching clock mode from PLL to DIV
When switching from PLL mode to DIV mode, the PLLCOUNT delay does not occur, and the switch between
the two modes takes place after a short transition delay.
The switch from PLL mode to DIV mode is also accomplished by loading the CLKMD register. The PLLNDIV
bit is set to 0, selecting DIV mode, and the PLLMUL bits are set to select the desired frequency multiplier as
shown in Table 6.
The switch to DIV mode takes effect in 6 CLKIN cycles plus 3.5 PLL cycles (CLKOUT frequency) for all PLLMUL
values except 1111b. With a PLLMUL value of 1111b, the switch to DIV mode takes effect in 12 CLKIN cycles
plus 3.5 PLL cycles (CLKOUT frequency). When the switch to DIV mode is completed, the PLLSTATUS bit in
the CLKMD register is read as 0.
The following software example shows a code sequence that can be used to switch from PLL
×
3 to
divide-by-two mode. Note that the PLLSTATUS bit is polled to determine when the switch to DIV mode has taken
effect, and then the STM instruction is used to turn off the PLL at this point.
STM
LDM
AND
BC
STM
#0b, CLKMD
CLKMD, A
#01b, A
TstStatu, ANEQ
#0b, CLKMD
;switch to DIV mode
TstStatu:
;poll STATUS bit
;reset PLLON_OFF when STATUS
;is DIV mode
switching mode from one PLL multiplier to another
When switching from one PLL multiplier ratio to another is required, the clock generator must be switched from
PLL mode to DIV mode before selecting the new multiplier ratio; switching directly from one PLL multiplier ratio
to another is not supported.
In order to switch from one PLL multiplier ratio to another, the following steps must be followed:
1.
Set the PLLNDIV bit to 0, selecting DIV mode.
2.
Poll the PLLSTATUS bit until a 0 is obtained, indicating that DIV mode is enabled.
3.
Modify the CLKMD register to set the PLLMUL[3–0], PLLDIV, and PLLNDIV bits to the desired frequency
multiplier as defined in Table 6, and the PLLCOUNT[7–0] bits to the required lock-up time.
When the PLLNDIV bit is set to one in step three, the PLLCOUNT timer begins decrementing from its preset
value. Once the PLLCOUNT timer reaches zero, the new PLL mode takes effect after six CLKIN cycles plus
3.5 PLL cycles (CLKOUT frequency).
A
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