參數(shù)資料
型號： TMS320LC545
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors(20/25ns指令周期， 高性能，大并行度，特殊指令集可有效實(shí)現(xiàn)多種復(fù)雜算法及應(yīng)用的DSP)
中文描述： 數(shù)字信號處理器（20/25ns指令周期，高性能，大并行度，特殊指令集可有效實(shí)現(xiàn)多種復(fù)雜算法及應(yīng)用的數(shù)字信號處理器）
文件頁數(shù)： 35/107頁
文件大小： 2149K
代理商： TMS320LC545
TMS320C54x, TMS320LC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039A – FEBRUARY 1996 – REVISED JULY 1997
32
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
software-programmable PLL (’545A, ’546A, and ’548) (continued)
Immediately following reset, the clock mode is determined by the values of the three external pins: CLKMD1,
CLKMD2, and CLKMD3. The modes corresponding to the CLKMD pins are shown in Table 7.
Table 7. Clock Mode Settings at Reset
CLKMD1
CLKMD2
CLKMD3
CLKMD REGISTER
RESET VALUE
CLOCK MODE
0
0
0
0000h
Divide-by-two, with external source
0
0
1
1000h
Divide-by-two, with external source
0
1
0
2000h
Divide-by-two, with external source
1
0
0
4000h
Divide-by-two, internal oscillator enabled
1
1
0
6000h
Divide-by-two, with external source
1
1
1
7000h
Divide-by-two, internal oscillator enabled
PLL
×
1 with external source
Stop mode
1
0
1
0007h
0
1
1
—
Following reset, the software-programmable PLL can be programmed to any configuration desired, as
described above. Note that when the PLL
×
1 with external source option (CLKMD[1–3]=101) is selected during
reset, the internal PLL lock-count timer is not active; therefore, the system must delay releasing reset in order
to allow for the PLL lock-time delay.
programming considerations when using the software-programmable PLL
The software-programmable PLL offers many different options in startup configurations, operating modes, and
power-saving features. Programming considerations and several software examples are presented here to
illustrate the proper use of the software-programmable PLL at start-up, when switching between different
clocking modes, and before and after IDLE1/IDLE2/IDLE3 instruction execution.
use of the PLLCOUNT programmable lock timer
During the lockup period, the PLL should not be used to clock the ’54x. The PLLCOUNT programmable lock
timer provides a convenient method of automatically delaying clocking of the device by the PLL until lock is
achieved.
The PLL lock timer is a counter, loaded from the PLLCOUNT field in the CLKMD register, that decrements from
its preset value to 0. The timer can be preset to any value from 0 to 255, and its input clock is CLKIN divided
by 16. The resulting lockup delay can therefore be set from 0 to 255
16 CLKIN cycles.
The lock timer is activated when the clock generator operating mode is switched from DIV to PLL (see the
section describing switching from DIV mode to PLL mode). During the lockup period, the clock generator
continues to operate in DIV mode; after the PLL lock timer has decremented to zero, the PLL begins clocking
the ’54x.
Accordingly, the value loaded into PLLCOUNT is chosen based on the following relationship:
PLLCOUNT
Lockup Time / (16
t
CLKIN
)
where t
CLKIN
is the input reference clock period and lockup time is the required PLL lockup time as shown in
Figure 7.
A
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