參數(shù)資料
型號: TMS320LC545
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processors(20/25ns指令周期, 高性能,大并行度,特殊指令集可有效實現(xiàn)多種復雜算法及應(yīng)用的DSP)
中文描述: 數(shù)字信號處理器(20/25ns指令周期,高性能,大并行度,特殊指令集可有效實現(xiàn)多種復雜算法及應(yīng)用的數(shù)字信號處理器)
文件頁數(shù): 15/107頁
文件大小: 2149K
代理商: TMS320LC545
TMS320C54x, TMS320LC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039A – FEBRUARY 1996 – REVISED JULY 1997
12
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
’C54x/’LC54x Signal Descriptions
TERMINAL
NAME
DESCRIPTION
TYPE
DATA SIGNALS
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
(MSB)
(LSB)
O/Z
Parallel port address bus A22 (MSB) through A0 (LSB). A15–A0 are multiplexed to address external
data/program memory or I/O. A15–A0 are placed in the high-impedance state in the hold mode. A15–A0 also
go into the high-impedance state when EMU1/OFF is low. A22 to A16 are used for extended program memory
addressing (’LC548 only).
On the ’LC548, the address bus has a feature called bus holder that eliminates passive components and the
power dissipation associated with it. The bus holder keeps the address bus at the previous logic level when the
bus goes into a high-impedance state.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(MSB)
(LSB)
I/O/Z
Parallel port data bus D15 (MSB) through D0 (LSB). D15–D0 are multiplexed to transfer data between the core
CPU and external data/program memory or I/O devices. D15–D0 are placed in the high-impedance state when
not output or when RS or HOLD is asserted. D15–D0 also go into the high-impedance state when EMU1/OFF
is low.
The data bus has a feature called bus holder that eliminates passive components and the power dissipation
associated with it. The bus holder keeps the data bus at the previous logic level when the bus goes into a
high-impedance state.
INITIALIZATION, INTERRUPT AND RESET OPERATIONS
IACK
O/Z
Interrupt acknowledge signal. IACK indicates the receipt of an interrupt and that the program counter is fetching
the interrupt vector location designated by A15–0. IACK also goes into the high-impedance state when
EMU1/OFF is low.
INT0
INT1
INT2
INT3
I = Input, O = Output, Z = High impedance
I
External user interrupt inputs. INT0 –INT3 are prioritized and are maskable by the interrupt mask register and
the interrupt mode bit. INT0 –INT3 can be polled and reset by the interrupt flag register.
A
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