參數(shù)資料
型號(hào): TMS320LC542-50
元件分類: 數(shù)字信號(hào)處理
英文描述: Digital Signal Processor
中文描述: 數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 44/111頁(yè)
文件大?。?/td> 1426K
代理商: TMS320LC542-50
TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999
44
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
status registers (ST0, ST1)
The status registers, ST0 and ST1, contain the status of the various conditions and modes for the ’54x devices.
ST0 contains the flags (OV, C, and TC) produced by arithmetic operations and bit manipulations in addition to
the data page pointer (DP) and the auxiliary register pointer (ARP) fields. ST1 contains the various modes and
instructions that the processor operates on and executes.
accumulators (AL, AH, AG, and BL, BH, BG)
The ’54x devices have two 40-bit accumulators: accumulator A and accumulator B. Each accumulator is
memory-mapped and partitioned into accumulator low-word (AL, BL), accumulator high-word (AH, BH), and
accumulator guard bits (AG, BG).
39
AH (BH)
AG (BG)
0
16 15
32 31
AL (BL)
auxiliary registers (AR0–AR7)
The eight 16-bit auxiliary registers (AR0–AR7) can be accessed by the CALU and modified by the auxiliary
register arithmetic units (ARAUs). The primary function of the auxiliary registers is generating 16-bit addresses
for data space. However, these registers also can act as general-purpose registers or counters.
temporary register (TREG)
The TREG is used to hold one of the multiplicands for multiply and multiply/accumulate instructions. It can hold
a dynamic (execution-time programmable) shift count for instructions with shift operation such as ADD, LD, and
SUB instructions. It also can hold a dynamic bit address for the BITT instruction. The EXP instruction stores the
exponent value computed into the TREG, while the NORM instruction uses the TREG value to normalize the
number. For ACS operation of Viterbi decoding, TREG holds branch metrics used by the DADST and DSADT
instructions.
transition register (TRN)
The TRN is a 16-bit register that is used to hold the transition decision for the path to new metrics to perform
the Viterbi algorithm. The CMPS (compare, select, max, and store) instruction updates the contents of the TRN
based on the comparison between the accumulator high word and the accumulator low word.
stack-pointer register (SP)
The SP is a 16-bit register that contains the address at the top of the system. The SP always points to the last
element pushed onto the stack. The stack is manipulated by interrupts, traps, calls, returns, and the PUSHD,
PSHM, POPD, and POPM instructions. Pushes and pops of the stack predecrement and postincrement,
respectively, all 16 bits of the SP.
circular-buffer-size register (BK)
The 16-bit BK is used by the ARAUs in circular addressing to specify the data block size.
block repeat registers (BRC, RSA, REA)
The block-repeat counter (BRC) is a 16-bit register used to specify the number of times a block of code is to
be repeated when performing a block repeat. The block-repeat start address (RSA) is a 16-bit register
containing the starting address of the block of program memory to be repeated when operating in the repeat
mode. The 16-bit block repeat-end address (REA) contains the ending address if the block of program memory
is to be repeated when operating in the repeat mode.
interrupt registers (IMR, IFR)
The interrupt-mask register (IMR) is used to mask off specific interrupts individually at required times. The
interrupt-flag register (IFR) indicates the current status of the interrupts.
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