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參數(shù)資料
| 型號： | TMS320LC542-50 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processor |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 26/111頁 |
| 文件大?。?/td> | 1426K |
| 代理商： | TMS320LC542-50 |
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TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999
26
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
program memory
The external program memory space on the ’54x devices addresses up to 64K 16-bit words. Software can
configure their memory cells to reside inside or outside of the program address map. When the cells are mapped
into program space, the device automatically accesses them when their addresses are within bounds. When
the program-address generation (PAGEN) logic generates an address outside its bounds, the device
automatically generates an external access. The advantages of operating from on-chip memory are as follows:
Higher performance because no wait states are required
Lower cost than external memory
Lower power than external memory
The advantage of operating from off-chip memory is the ability to access a larger address space.
program memory address map
The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that
the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the
code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch
instruction, and either two 1-word instructions or one 2-word instruction, which allows branching to the
appropriate interrupt service routine without the overhead.
At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However,
these vectors can be remapped to the beginning of any 128-word page in program space after device reset.
This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate
128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new
128-word page. For example:
STM
This example moves the interrupt vectors to program space at address 05800h. Any subsequent interrupt
(except for a device reset) fetches its interrupt vector from that new location. For example, if, after loading the
IPTR, an INT2 occurs, the interrupt service routine vector is fetched from location 5848h in program space as
opposed to location FFC8h. This feature facilitates moving the desired vectors out of the boot ROM and then
removing the ROM from the memory map. Once the system code is booted into the system from the boot-loader
code resident in ROM, the application reloads the IPTR with a value pointing to the new vectors. In the previous
example, the STM instruction is used to modify the PMST. Note that the STM instruction modifies not only the
IPTR but other status/control bits in the PMST register.
#05800h,PMST
;Remapped vectors to start at 5800h.
NOTE: The hardware reset (RS) vector cannot be remapped, because the hardware reset loads the IPTR with
1s. Therefore, the reset vector is always fetched at location FF80h in program space. In addition, for the ’54x,
128 words are reserved in the on-chip ROM for device-testing purposes. Application code written to be
implemented in on-chip ROM must reserve these 128 words at addresses FF00h–FF7Fh in program space.
extended program memory (’548 and ’549 only)
The ’548 and ’549 devices use a paged extended memory scheme in program space to allow access of up to
8M of program memory. This extended program memory is organized into 128 pages (0–127), each 64K in
length. To implement the extended program memory scheme, the ’548 and ’549 device includes the following
additional features:
Seven additional address lines (for a total of 23)
An extra memory-mapped register [program counter extension register (XPC)]
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| TMS320LC542PBK1-50 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320LC542PBK2-50 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320LC542PGE1-40 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320LC542PGE1-50 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320LC542PGE2-40 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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