參數(shù)資料
型號(hào)： TMS320F241PGS
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 0-BIT, 5 MHz, OTHER DSP, PQFP64
封裝： PLASTIC, QFP-64
文件頁(yè)數(shù)： 80/122頁(yè)
文件大?。?/td> 1465K
代理商： TMS320F241PGS
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TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064D DECEMBER 1997 REVISED FEBRUARY 2006
60
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
controller area network (CAN) module (continued)
Table 17. Register Addresses
Address
Name
Description
7100h
MDER
Mailbox Direction/Enable Register (bits 7 to 0)
7101h
TCR
Transmission Control Register (bits 15 to 0)
7102h
RCR
Receive Control Register (bits 15 to 0)
7103h
MCR
Master Control Register (bits 13 to 6, 1, 0)
7104h
BCR2
Bit Configuration Register 2 (bits 7 to 0)
7105h
BCR1
Bit Configuration Register 1 (bits 10 to 0)
7106h
ESR
Error Status Register (bits 8 to 0)
7107h
GSR
Global Status Register (bits 5 to 0)
7108h
CEC
Transmit and Receive Error Counters (bits 15 to 0)
7109h
CAN_IFR
Interrupt Flag Register (bits 13 to 8, 6 to 0)
710Ah
CAN_IMR
Interrupt Mask Register (bits 15, 13 to 0)
710Bh
LAM0_H
Local Acceptance Mask for MBOX0 and 1 (bits 31, 28 to 16)
710Ch
LAM0_L
Local Acceptance Mask for MBOX0 and 1 (bits 15 to 0)
710Dh
LAM1_H
Local Acceptance Mask for MBOX2 and 3 (bits 31, 28 to 16)
710Eh
LAM1_L
Local Acceptance Mask for MBOX2 and 3 (bits 15 to 0)
710Fh
Reserved
Accesses assert the CAADDRx signal from the CAN peripheral (which will assert an Illegal Address error)
All unimplemented register bits are read as zero, writes have no effect. Register bits are initialized to zero, unless otherwise stated in the definition.
CAN interrupt logic
There are two interrupt requests from the CAN module to the Peripheral Interrupt Expansion (PIE) controller:
the Mailbox Interrupt and the Error Interrupt. Both interrupts can assert either a high-priority request or a
low-priority request to the CPU. The following events can initiate an interrupt:
D Transmission Interrupt
A message was transmitted or received successfully — asserts the Mailbox Interrupt.
D Abort Acknowledge Interrupt
A send transmission was aborted — asserts the Error Interrupt.
D Write Denied Interrupt
The CPU tried to write to a mailbox but was not allowed to — asserts the Error Interrupt.
D Wakeup Interrupt
After wakeup, this interrupt is generated — asserts the Error Interrupt, even when clocks are not running.
D Receive Message Lost Interrupt
An old message was overwritten by a new one — asserts the Error Interrupt.
D Bus-Off Interrupt
The CAN module enters the bus-off state — asserts the Error Interrupt.
D Error Passive Interrupt
The CAN module enters the error passive mode — asserts the Error Interrupt.
D Warning Level Interrupt
One or both of the error counters is greater than or equal to 96 — asserts the Error Interrupt.
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