參數(shù)資料
型號： TMS320F241PGS
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號處理
英文描述： 0-BIT, 5 MHz, OTHER DSP, PQFP64
封裝： PLASTIC, QFP-64
文件頁數(shù)： 13/122頁
文件大?。?/td> 1465K
代理商： TMS320F241PGS
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064D DECEMBER 1997 REVISED FEBRUARY 2006
11
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Terminal Functions - F243 PGE Package (Continued)
NAME
144
LQFP
TYPE
RESET
STATE
DESCRIPTION
NAME
NO.
TYPE
STATE
DESCRIPTION
INTERRUPT, EXTERNAL ACCESS, AND MISCELLANEOUS SIGNALS (CONTINUED)
PMT
68
I
Enables parallel module test (PMT). This pin must be connected to ground.
(
↓)
VCCP/WDDIS
77
I
Flash programming voltage pin and watchdog disable. This is the 5-V supply used
for flash programming. Flash cannot be programmed if this pin is held at 0 V. This
pin also works as a hardware watchdog disable, when VCCP/WDDIS = +5 V and
bit 6 in WDCR is set to 1. Do not use a current-limiting resistor on this pin.
DEDICATED I/O SIGNALS
IOPD2
20
I/O
Dedicated GPIO Port D bit 2
(
↓)
IOPD3
21
I/O
Dedicated GPIO Port D bit 3
(
↓)
IOPD4
23
I/O
I
Dedicated GPIO Port D bit 4
(
↓)
IOPD5
25
I/O
I
Dedicated GPIO Port D bit 5
(
↓)
IOPD6
27
I/O
Dedicated GPIO Port D bit 6
(
↓)
IOPD7
29
I/O
Dedicated GPIO Port D bit 7
(
↓)
DATA AND ADDRESS BUS SIGNALS
D0
(
↓)
33
D1
(
↓)
35
D2
(
↓)
38
D3
(
↓)
46
D4
(
↓)
48
D5
(
↓)
50
D6
(
↓)
52
D7
(
↓)
54
I/O/Z
O§
Bit x of the 16-bit Data Bus
D8
(
↑)
57
I/O/Z
O§
Bit x of the 16-bit Data Bus
D9
(
↓)
59
D10
(
↓)
61
D11
(
↓)
63
D12
(
↓)
65
D13
(
↓)
67
D14
(
↓)
69
D15
(
↓)
71
I = input, O = output, Z = high impedance
The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is
an output, its level at reset is indicated.
§ At reset, the device comes up with AVIS mode enabled. The data bus is in output mode while AVIS is enabled.
NOTE: Bold, italicized pin names indicate pin function after reset.
LEGEND:
↑ Internal pullup
↓ Internal pulldown
(Typical active pullup/pulldown value is 150
A.)
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