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參數(shù)資料
| 型號： | TMS320F241PGS |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 0-BIT, 5 MHz, OTHER DSP, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數(shù)： | 48/122頁 |
| 文件大?。?/td> | 1465K |
| 代理商： | TMS320F241PGS |
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TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064D DECEMBER 1997 REVISED FEBRUARY 2006
31
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
interrupt request structure
1.
At the lower level of the hierarchy, the peripheral interrupt requests (PIRQs) from several peripherals to the
interrupt controller are ORed together to generate a request to the CPU. There is an interrupt flag bit and
an interrupt enable bit located in the peripheral for each event that can cause a peripheral interrupt request.
There is also one PIRQ for each event. If an interrupt-causing event occurs in a peripheral, and the
corresponding interrupt enable bit is set, the interrupt request from the peripheral to the interrupt controller
is asserted. This interrupt request simply reflects the status of the peripheral’s interrupt flag gated with the
interrupt enable bit. When the interrupt flag is cleared, the interrupt request is cleared. Some peripherals
have the capability to make either a high-priority or a low-priority interrupt request. If a peripheral has this
capability, the value of its interrupt priority bit is transmitted to the interrupt controller. The interrupt request
continues to be asserted until it is either automatically cleared by an interrupt acknowledge or cleared by
software.
2.
At the upper level of the hierarchy, the ORed PIRQs generate interrupt (INT) requests to the CPU. The
request to the 24x CPU is a low-going pulse of 2 CPU clock cycles. The Peripheral Interrupt Expansion (PIE)
controller generates an INT pulse when any of the PIRQs controlling that INT go active. If any of the PIRQs
capable of asserting that CPU interrupt request are still active in the cycle following an interrupt
acknowledge for that INT, another INT pulse is generated (an interrupt acknowledge clears the
highest-priority pending PIRQ). Which CPU interrupt requests get asserted by which peripheral interrupt
requests, and the relative priority of each peripheral interrupt request, is defined in the interrupt controller
and is not part of any of the peripherals. This is shown in Table 10.
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