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參數(shù)資料
| 型號(hào)： | TMS320F241PGS |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 0-BIT, 5 MHz, OTHER DSP, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數(shù)： | 76/122頁 |
| 文件大?。?/td> | 1465K |
| 代理商： | TMS320F241PGS |
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TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064D DECEMBER 1997 REVISED FEBRUARY 2006
57
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
serial communications interface (SCI) module
The F243/F241 devices include a serial communications interface (SCI) module. The SCI module supports
digital communications between the CPU and other asynchronous peripherals that use the standard
non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own
separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex
mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing
errors. The bit rate is programmable to over 65 000 different speeds through a 16-bit baud-select register.
Features of the SCI module include:
D Two external pins
SCITXD: SCI transmit-output pin
SCIRXD: SCI receive-input pin
NOTE:
Both pins can be used as GPIO if not used for SCI.
D Baud rate programmable to 64K different rates
Up to 1250 Kbps at 20-MHz CPUCLK
D Data word format
One start bit
Data word length programmable from one to eight bits
Optional even/odd/no parity bit
One or two stop bits
D Four error-detection flags: parity, overrun, framing, and break detection
D Two wake-up multiprocessor modes: idle-line and address bit
D Half- or full-duplex operation
D Double-buffered receive and transmit functions
D Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and
TX EMPTY flag (transmitter-shift register is empty)
Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR (monitoring four interrupt conditions)
D Separate enable bits for transmitter and receiver interrupts (except BRKDT)
D NRZ (non-return-to-zero) format
D Ten SCI module control registers located in the control register frame beginning at address 7050h
NOTE: All registers in this module are 8-bit registers that are connected to the 16-bit peripheral bus. When a register is accessed, the register
data is in the lower byte (7 0), and the upper byte (15 8) is read as zeros. Writing to the upper byte has no effect.
Figure 13 shows the SCI module block diagram.
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