參數(shù)資料
型號: TMS320C10-25
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processors(160ns指令周期,分離的程序和數(shù)據(jù)總線,外部輪詢中斷的DSP)
中文描述: 數(shù)字信號處理器(160ns指令周期,分離的程序和數(shù)據(jù)總線,外部輪詢中斷的數(shù)字信號處理器)
文件頁數(shù): 85/139頁
文件大小: 1478K
代理商: TMS320C10-25
TMS320C16
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443
HOUSTON, TEXAS 77001
85
MEMORY AND PERIPHERAL INTERFACE TIMING
switching characteristics over recommended operating conditions
PARAMETER
MIN
NOM
MAX
UNIT
td1
td2
td3
td4
td5
td6
td7
td8
td9(CLK)
td9(MEN)
td10(CLK)
td10(WE)
tv
th(A-WMD)
tsu(A-MD)
Delay time, MEN
, MWE
, IOEN
, IOWE
, to next address bus valid
0
35
ns
Delay time, CLKOUT
to MEN
1/4tc(C)– 5
– 3
1/4tc(C)– 5
– 3
1/2tc(C)– 5
– 3
1/4tc(C)+12
ns
Delay time, CLKOUT
to MEN
6
ns
Delay time, CLKOUT
to IOEN
1/4tc(C)+12
ns
Delay time, CLKOUT
to IOEN
6
ns
Delay time, CLKOUT
to MWE
, IOWE
1/2tc(C)+12
ns
Delay time, CLKOUT
to MWE
, IOWE
6
ns
Delay time, MWE
, IOwE
, data bus out valid
0
ns
Delay time, CLKOUT
to data bus starts to be driven
1/4tc(C)– 5
1/4tc(C)
ns
Delay time, MEN
, to data bus starts to be driven
ns
Delay time, CLKOUT
to data bus stops being driven
15
ns
Delay time, MWE
, IOWE
, data bus stops being driven
20
ns
Data bus OUT valid after MWE
, IOWE
5
10
ns
Address bus hold time after MWE
, MEN
, IOWE
, or IOEN
0
2
ns
Address bus setup time prior to MEN
, IOEN
5
ns
timing requirements over recommended operating conditions
MIN
35
MAX
UNIT
ns
tsu(D)
th(D)
Setup time, data bus valid prior to MEN
, IOEN
Hold time, data bus held valid after MEN
, IOEN
0
ns
RESET (RS) TIMING
switching characteristics over recommended operating conditions
PARAMETER
MIN
MAX
UNIT
ns
td11
tdis(R)
Delay time, IOEN
, IOWE
, MWE
, and MEN
from RS
1/2tc(C)+50
1/4tc(C)+50
Data bus disable time after RS
ns
timing requirements over recommended operating conditions
MIN
MAX
UNIT
tsu(R)
tw(R)
Reset (RS) setup time prior to CLKOUT
30
ns
RS pulse duration
5tc(C)
ns
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