參數(shù)資料
型號: TMP96C141AF
廠商: Toshiba Corporation
英文描述: High Speed Advanced CMOS 16-bit Microcontroller For Controlling Medium to Large-Scale Equipment(用于中等到大型設(shè)備控制,高速、先進的 CMOS 16位微控制器)
中文描述: 采用先進的CMOS高速16位微控制器控制中的大型設(shè)備(用于中等到大型設(shè)備控制,高速,先進的的CMOS 16位微控制器)
文件頁數(shù): 73/178頁
文件大小: 5667K
代理商: TMP96C141AF
TOSHIBA CORPORATION
73
TMP96C141AF
TREG2 and TREG3 are controlled double buffer
enable/disable by P0MOD <DB2EN> and P1MOD
<DB3EN> : disabled when <DB2EN>/<DB3EN> = 0,
enabled when <DB2EN>/<DB3EN> = 1.
Data is transferred from register buffer to timer when a
2
n
- 1 overflow occurs in the PWM mode, or when
compare and match occurs in 8-bit timer mode. That
is, with a PWM timer, the timer mode can be operated
Figure 3.8 (3). Structure of Timer Registers 2 and 3
in double buffer enable state, unlike timer mode for
timers 0 and 1.
At reset, <DB2EN>/<DB3EN> is initialized to 0 to dis-
able double buffer. To use double buffer, write the data
in the timer register at first, then set <DB2EN>/
<DB3EN> to 1, and write the following data in the reg-
ister buffer.
Note:
The timer register and register buffer are allocated to the same
memory address. When <DB2EN>/<DB3EN> = 0, the same value
is written to both register buffer and timer register. When <DB2EN>/
<DB3EN> = 1, the value is written to the register buffer only.
Memory addresses of the timer registers are as follows:
TREG2 : 000026H
TREG3 : 000027H
Both timer registers are write only; however, register
buffer values can be read when reading the above
addresses.
Comparator
Compares the value in the up-counter with the value in
the timer register (TREG2/TREG3). When they match,
the comparator outputs the match detect signal. A
timer interrupt (INTT2/INTT3) is generated at compare
and match if the interrupt select bit <PWM01NT>/
<PWM1NT> of the mode register (P0MOD/P1MOD) is
set to 1. In timer mode, the comparator clears the up-
counter to 0 at compare and match. It also inverts the
value of the timer flip-flop if timer flip-flop invert is
enabled.
Timer flip-flop
The value of the timer flip-flop is inverted by the match
detect signal (comparator output) of each interval timer
or 2
n
- 1 overflow. The value can be output to the timer
output pin TO2/TO3 (also used as P72/P73).
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