參數(shù)資料
型號： TMP96C141AF
廠商： Toshiba Corporation
英文描述： High Speed Advanced CMOS 16-bit Microcontroller For Controlling Medium to Large-Scale Equipment(用于中等到大型設備控制，高速、先進的 CMOS 16位微控制器)
中文描述： 采用先進的CMOS高速16位微控制器控制中的大型設備（用于中等到大型設備控制，高速，先進的的CMOS 16位微控制器）
文件頁數(shù)： 129/178頁
文件大小： 5667K
代理商： TMP96C141AF
TOSHIBA CORPORATION
129
TMP96C141AF
2) Asynchronous Communication (UART) mode
The receiving control has a circuit for
detecting the start bit by the rule of majority.
When two or more “0” are detected during 3
samples, it is recognized as start bit and the
receiving operation is started.
Data being received is also evaluated by
the rule of majority.
Receiving Buffer
To prevent overrun error, the receiving buffer has a
double buffer structure.
Received data is stored one bit by one bit in the
receiving buffer 1 (shift register type). When 7 bits or 8
bits of data are stored in the receiving buffer 1, the stored
data is transferred to another receiving buffer 2 (SC0BUF/
SC1BUF), generating an interrupt INTRX0/INTRX1. The
CPU reads only receiving buffer 2 (SC0BUF/SC1BUF).
Even before the CPU reads the receiving buffer 2
(SC0BUF/SC1BUF), the received data can be stored in
the receiving buffer 1. However, unless the receiving
buffer 2 (SC0BUF/SC1BUF) is read before all bits of the
next data are received by the receiving buffer 1, an over-
run error occurs. If an overrun error occurs, the contents
of the receiving buffer 1 will be lost, although the contents
of the receiving buffer 2 and SC0CR <RB8> SC1CR
<RB8> are still preserved.
The parity bit added in 8-bit UART mode and the
most significant bit (MSB) in 9-bit UART mode are stored
in SC0CR <RB8>/SC1CR <RB8>.
When in 9-bit UART mode, the wake-up function of
the slave controllers is enabled by setting SC0MOD
<WU>/SC1MOD <WU> to “1", and interrupt INTRX0/
INTRX1 occurs only when SC0CR <RB8>/SC1CR
<RB8> is set to “1”.
Transmission Counter
Transmission counter is a 4-bit binary counter which
is used in asynchronous communication (UART) mode
and, like a receiving counter, counts by SIOCLK clock,
generating TxDCLK every 16 clock pulses.
Figure 3.11 (14). Generation of Transmission Clock
Transmission Controller
1) I/O interface mode (channel 1 only)
In SCLK output mode with the setting of
SC1CR <IOC> = “0", the data in the trans-
mission buffer are output bit by bit to TxD1
pin at the rising edge of shift clock which is
output from SCLK1 pin.
In SCLK input mode with the setting
SC1CR <IOC> = “1", the data in the trans-
mission buffer are output bit by bit to TxD1
pin at the rising edge or falling edge of SCLK
input according to the setting of SC1CR
<SCLKC> register.
2) Asynchronous Communication (UART) mode
When transmission data is written in the
transmission buffer sent from the CPU, trans-
mission starts at the rising edge of the next
TxDCLK, generating a transmission shift
clock TxDSFT.
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相關代理商/技術參數(shù)
參數(shù)描述
TMP96C141BF 功能描述:16位微控制器 - MCU ROMLESS TLCS 900 w/ 1K RAM RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風格:SMD/SMT
TMP96C141BFG 功能描述:16位微控制器 - MCU 900 Romless MCU 1K RAM RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風格:SMD/SMT
TMP96CM40F 制造商:Toshiba America Electronic Components 功能描述:TLCS900 M/ROM, 32K ROM , 1K RAM - Tape and Reel
TMP96PM40F 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:Quality And Reliability Assurance / Handling Precautions
TMP96PM40F(Z) 功能描述:16位微控制器 - MCU 32K ROM OTP 1K RAM RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風格:SMD/SMT
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