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參數(shù)資料
| 型號(hào)： | TMP96C031 |
| 廠商： | Toshiba Corporation |
| 英文描述： | High Speed Advanced CMOS 16-bit Microcontroller For Controlling Medium to Large-Scale Equipment(用于中等到大型設(shè)備控制，高速、先進(jìn)的 CMOS 16位微控制器) |
| 中文描述： | 采用先進(jìn)的CMOS高速16位微控制器控制中的大型設(shè)備（用于中等到大型設(shè)備控制，高速，先進(jìn)的的CMOS 16位微控制器） |
| 文件頁(yè)數(shù)： | 63/186頁(yè) |
| 文件大?。?/td> | 5299K |
| 代理商： | TMP96C031 |
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TOSHIBA CORPORATION
63
TMP96C031N/F
Up-counter
This is an 8-bit binary counter counted by an input
clock specified by mode register T01MOD for timers 0
and 1, or mode register T23MOD for timers 2 and 3.
Input clocks for timer 0 or 2 can be selected from internal
clocks
φ
T1,
φ
T4, and
φ
T16 depending to the value set in
the TI0 pin can also be selected.
The input clock of timer 1 or 3 depends on the oper-
ation mode; in 16-bit timer mode, timer 0/2 overflow out-
put is used as the output clock. When set to any other
mode than 16-bit timer mode, the input clock is selected
from the internal clocks
φ
T1,
as the comparator output (match detection signal) of
timer 0 according to the set value of T01MOD register or
T23MOD.
φ
T16, and
φ
T256 as well
Example: When T01MOD <T01M1,0> = 01, the over
flow output of timer 0 becomes the input
clock of timer 1 (16-bit timer).
When T01MOD7, 6 = 00, T01MOD3, 2 =
01,
φ
T1 (8/fc) becomes the input of timer
1 (8-bit timer).
Operation mode is also set by T01MOD register and
T23MOD register. When reset, it is initialized to T01MOD
<T01M1, 0> = 00, T23MOD <T23M1, 0> = 00 whereby
the up-counter is placed in the 8-bit timer mode.
The counting and stop and clear of up-counter can
be controlled for each interval timer by the timer opera-
tion control register TRUN. When reset, all up-counters
will be cleared to stop the timers.
Timer register
This is an 8-bit register for setting an interval time.
When the set value of timer registers TREG0, TREG1,
TREG2, TREG3 matches the value of up-counter, the
comparator match detect signal becomes active. If the
set value is 00H, this signal becomes active when the up-
counter overflows.
Timer register TREG0/TREG2 is of double buffer
structure, each of which makes a pair with register buffer.
TREG0/TREG2 is used to control enable/disable of
the double buffers according to the timer register double
buffer control register, TRDC <TR0DE, TR2DE>. It is dis-
abled when <TR0DE>/<TR2DE> = 0 and enabled when
they are set to 1.
In the condition of double buffer enable state, the
data is transferred from the register buffer to the timer
register when the 2
- 1 overflow occurs in PWM mode,
or at the PPG cycle in PPG mode.
When reset, it will be initialized to <TR0DE>/
<TR2DE> = 0 to disable the double buffer. To use the
double buffer, write data in the timer register, set
<TR0DE>/<TR2DE> to 1, and write the following data in
the register buffer.
n
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMP96C031F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microcontroller |
| TMP96C031N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microcontroller |
| TMP96C031ZF | 制造商:Toshiba America Electronic Components 功能描述:MCU 16BIT TLCS-900 CISC ROMLESS 5V 64PQFP - Bulk |
| TMP96C041AF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microcontroller |
| TMP96C041AFG | 制造商:Toshiba America Electronic Components 功能描述: |
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