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參數(shù)資料
| 型號(hào)： | TMP96C031 |
| 廠商： | Toshiba Corporation |
| 英文描述： | High Speed Advanced CMOS 16-bit Microcontroller For Controlling Medium to Large-Scale Equipment(用于中等到大型設(shè)備控制，高速、先進(jìn)的 CMOS 16位微控制器) |
| 中文描述： | 采用先進(jìn)的CMOS高速16位微控制器控制中的大型設(shè)備（用于中等到大型設(shè)備控制，高速，先進(jìn)的的CMOS 16位微控制器） |
| 文件頁(yè)數(shù)： | 16/186頁(yè) |
| 文件大?。?/td> | 5299K |
| 代理商： | TMP96C031 |
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TOSHIBA CORPORATION
TMP96C031N/F
3.3.3 Interrupt Controller
Figure 3.3.3 (1) is a block diagram of the interrupt circuits. The
left half of the diagram shows the interrupt controller; the right
half includes the CPU interrupt request signal circuit and the
HALT release signal circuit.
Each interrupt channel (total of 20 channels) in the inter-
rupt controller has an interrupt request flip-flop, interrupt prior-
ity setting register, and a register for storing the high-speed
micro DMA start vector. The interrupt request flip-flop is used
to latch interrupt requests from peripheral devices. The flip-flop
is cleared to 0 at reset, when the CPU reads the interrupt
channel vector after the acceptance of interrupt, or when the
CPU executes an instruction that clears the interrupt of that
channel (writes 0 in the clear bit of the interrupt priority setting
register).
For example, to clear the INT0 interrupt request, set the
register after the DI instruction as follows.
INTE0AD
←
---- 0 ---
Zero-clears the INT0 Flip Flop.
The status of the interrupt request flip-flop is detected by
reading the clear bit. Detects whether there is an interrupt
request for an interrupt channel.
The interrupt priority can be set by writing the priority in
the interrupt priority setting register (e.g., INTE0AD, INTE45,
etc.) provided for each interrupt source. Interrupt levels to be
set are from 1 to 6. Writing 0 or 7 as the interrupt priority dis-
ables the corresponding interrupt request. The priority of the
non-maskable interrupt (NMI pin, watchdog timer, etc.) is fixed
to 7. If interrupt requests with the same interrupt level are gen-
erated simultaneously, interrupts are accepted in accordance
with the default priority (the smaller the vector value, the higher
the priority).
The interrupt controller sends the interrupt request with
the highest priority among the simultaneous interrupts and its
vector address to the CPU. The CPU compares the priority
value <IFF2 to 0> set in the Status Register by the interrupt
request signal with the priority value sent; if the latter is higher,
the interrupt is accepted. Then the CPU sets a value higher
than the priority value by 1 in the CPU SR <IFF2 to 0>. Inter-
rupt requests where the priority value equals or is higher than
the set value are accepted simultaneously during the previous
interrupt routine. When interrupt processing is completed (after
execution of the RETI instruction), the CPU restores the priority
value saved in the stack before the interrupt was generated to
the CPU SR <IFF2 to 0>.
The interrupt controller also has four registers used to
store the high-speed other
μ
DMA start vector. These are I/O
registers; unlike other DMA registers (DMAS, DMAD, DMAM,
and DMAC), they can be accessed in either normal or system
mode. Writing the start vector of the interrupt source for the
μ
DMA processing (see Table 3.3 (1)), enables the correspond-
ing interrupt to be processed by
must be set in the
μ
DMA parameter registers (e.g., DMAS and
DMAD) prior to the
μ
DMA processing.
μ
DMA processing. The values
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMP96C031F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microcontroller |
| TMP96C031N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microcontroller |
| TMP96C031ZF | 制造商:Toshiba America Electronic Components 功能描述:MCU 16BIT TLCS-900 CISC ROMLESS 5V 64PQFP - Bulk |
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| TMP96C041AFG | 制造商:Toshiba America Electronic Components 功能描述: |
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