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TOSHIBA CORPORATION
TMP96C031N/F
2.2 Pin Names and Functions
The names of input/output pins and their functions are described below.
Note:
The internal I/O of this device cannot be accessed using the external DMA controller.
Table 2.2. Pin Names and Functions
Pin Name
Number
of Pins
I/O
Functions
AD0 ~ AD7
AD8 ~ AD15
A8 ~ A15
P20 ~ P27
A0 ~ A7
A16 ~ A23
P30
TO5
HWR
P31
TI0
WAIT
8
Tri-state
Tri-state
Output
I/O
Output
Output
I/O
Output
Output
I/O
Output
Output
Address/data (lower): 0 - 7 for address/data bus
Address data (upper): 8 - 15 for address/data bus
Address: 8 to 15 for address bus
Port 2: I/O port that allows selection of I/O on a bit basis (with pull-down resistor)
Address: 0 - 7 for address bus
Address: 16 - 23 for address bus
Port 30: Output port (with pull-up register)
Timer output 5: Timer 4 output pin
High write: Strobe signal for writing data on pins AD8 - 15
Port 31: Output port (with pull-up register)
Timer output 0: Timer 0 input
Write: Pin used to request CPU bus wait
Port 32: I/O port (with pull-up register)
Bus request: Signal used to request high impedance for AD0 - 15, A0 - 23, RD, WR, HWR, R/W, RAS, CS0,
CS1, and CS2 pins. (For external DMAC)
Port 33: I/O port (with pull-up register)
Bus acknowledge: Strobe indicating that AD0 - 15, A0 - 23, RD, WR, HWR, R/W, RAS, CS0, CS1, and CS2
pins are at high impedance after receiving BUSRQ.
Port 34: I/O (with pull-up register)
Read/write: 1 represents read or dummy cycle 0, write cycle.
Non-maskable interrupt request pin; Interrupt request pin with falling edge. Can also be operated at rising
edge by program.
Port 35: I/O (with pull-up register)
Row address strobe: Outputs RAS strobe for DRAM.
Interrupt request pin 7: Interrupt request pin with rising edge.
Port 40: I/O port
Chip select 0: Outputs 0 when address is within specified address area.
Port 41: Output port
Chip select 1: Outputs 0 if address is within specified address area.
8
8
1
1
P32
BUSRQ
1
I/O
Input
P33
BUSAK
1
I/O
Input
P34
R/W
NMI
1
I/O
Output
Input
P35
RAS
INT7
P40
CS0
P41
CS1
P42
CS2
P43
CS3
CAS
P50 ~ P53
AN0 ~ AN3
INT1 ~ INT3
1
I/O
Output
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
1
1
1
Port 42: Output port
Chip select 2: Outputs 0 if address is within specified address area.
Port 43: Output port
Chip select 3: Outputs 0 if address is within specified address area.
Column address strobe 2: Outputs CAS strobe for DRAM if address is within specified address area.
Port 50 ~ 53: Input port
Analog input: Input to A/D converter
Interrupt request pin 0: Interrupt request pin with programmable level/rising edge.
Interrupt request pin 1: Interrupt request pin with programmable rising/falling edge.
Interrupt request pin 2 ~ 3: Interrupt request pin with rising edge.
Port 60: I/O port
Serial send data 0
Pattern generator port 00
Port 61: I/O port
Serial receive data 0
Pattern generator port 01
1
4
P60
TxD0
PG00
P61
RxD0
PG01
1
I/O
Output
Output
I/O
Output
Output
1