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參數(shù)資料
| 型號： | TLC320AD50CDW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | PLASTIC, SO-28 |
| 文件頁數(shù)： | 16/56頁 |
| 文件大?。?/td> | 555K |
| 代理商： | TLC320AD50CDW |
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2–8
2.7.1
Frame Sync (FS) Function, Master Mode
The frame sync is generated internally and goes low on the rising edge of SCLK and remains low during a 16-bit data
transfer. In addition to generating its own frame-sync signal, the master also outputs a frame sync for each slave that
is being used (see Figures 2–8 and 2–9).
FS
(see Note A)
DIN/DOUT
16 SCLKs
Primary
Secondary
Primary
128 SCLKs
256 SCLKs
SCLK
Primary
FS
(see Note B)
NOTES: A. Primary and secondary serial communication
B. Primary serial communication, only
Figure 2–8. Master Device Frame-Sync Signal With Primary and Secondary Communications
(No Slaves)
FS
(see Note A)
MP
128 SCLKs
256 SCLKs
SCLK
FS
(see Note B)
MP
SP
MS
SP
SS
MP
Delay is
m Shift Clocks
(see Note C)
MP
Legend:
MP: Master Primary (master device data is transferred in this period, DOUT of the slave device is in high impedance state).
SP: Slave Primary (slave device data is transferred in this period, DOUT of master device is in high impedance state).
MS: Master Secondary (master device control register information is transferred in this period, DOUT of the slave device is in high impedance state).
SS: Slave Secondary(slave device control register information is transferred in this period, DOUT of the master device is in high impedance state).
NOTES: A. Primary and secondary serial communications
B. Primary serial communication only
C.
m is the value programmed into the FSD register (control register 3: D0 –D5)
Figure 2–9. Master Device Frame-Sync Signal With Primary and Secondary Communications
(With 1 Slave Device)
2.7.2
Frame Sync (FS) Function,Slave Mode
Frame-sync timing is generated externally by the master FSD (or the previous slave in a multislave configuration)
and is applied to FS of the slave to control the ADC and DAC timing.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TLC320AD50CDWR | 功能描述:接口—CODEC SNGL CH Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLC320AD50C-I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION |
| TLC320AD50CPT | 功能描述:接口—CODEC SNGL CH Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLC320AD50CPTR | 功能描述:接口—CODEC SNGL CH Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLC320AD50I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION |
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