參數資料
型號： TLC320AD50CDW
廠商： TEXAS INSTRUMENTS INC
元件分類： 模擬信號調理
英文描述： SPECIALTY ANALOG CIRCUIT, PDSO28
封裝： PLASTIC, SO-28
文件頁數： 14/56頁
文件大?。?/td> 555K
代理商： TLC320AD50CDW
2–6
2.2
Reset and Power-Down Functions
2.2.1
Software and Hardware Reset
The TLC320AD50C and TLC320AD52C reset the internal counters and registers in response to either of two events:
1.
A low-going reset pulse is applied to terminal RESET.
2.
A 1 is written to the programmable software reset bit (D7 of control register 1).
Either event resets the control registers and clears all the sequential circuits in the device. Reset signals should be
at least 6 master clock periods long.
After hardware reset, the default contents of all registers is 0.
After a hardware or software reset, the AD50 and AD52 require a finite amount of time for the internal PLL to stabilize.
During this time, no control words or D/A data should be written to the device.
The reset sequence should be as follows:
1.
Assert reset (pulse width encompassing at least 6 MCLK periods)
2.
Deactivate reset
3.
Wait for SCLKS to be generated by the master device. This will take approximately 100
s.
4.
Wait for 18 frame syncs to occur
5.
Write control and configuration data
6.
Collect conversion data
2.2.2
Software and Hardware Power Down
Except for the digital interface, most of the device enters the power-down mode when D6 in control 1 register is set
to 1. When PWRDWN is taken low, the entire device is powered down. In either case, the register contents are
preserved and the output of the monitor amplifier is held at the midpoint voltage to minimize pops and clicks.
The amount of power drawn during software power down is higher than it is during a hardware power down because
of the current required to keep the digital interface active. Additional differences between software and hardware
power-down modes are detailed in the following paragraphs. Figure 2–7 represents the internal power-down logic.
PWRDWN
D6 is Programmed
Through a Secondary
Write Operation
Software Power Down
(Control Register 1, D6)
Internal TLC320AD50C
Figure 2–7. Internal Power-Down Logic
2.2.2.1 Software Power Down
When D6 of control 1 register is set to 1, the device enters the software power-down mode. In this state, the digital
interface circuit is still active while the internal ADC and DAC channels and differential outputs OUTP and OUTM are
disabled, and DOUT and FSD are inactive. Register data in the secondary serial communications is still accepted,
but data in the primary serial communications is ignored. The device returns to normal operation when D6 of control
1 register is reset to 0.
相關PDF資料
PDF描述
TLC320AD52CDWR SPECIALTY ANALOG CIRCUIT, PDSO28
TLC320AD50IDW SPECIALTY ANALOG CIRCUIT, PDSO28
TLC320AD50CPTR SPECIALTY ANALOG CIRCUIT, PQFP48
TLC320AD50IPTR SPECIALTY ANALOG CIRCUIT, PQFP48
TLC320AD50IPT SPECIALTY ANALOG CIRCUIT, PQFP48
相關代理商/技術參數
參數描述
TLC320AD50CDWR 功能描述:接口—CODEC SNGL CH Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLC320AD50C-I 制造商:TI 制造商全稱:Texas Instruments 功能描述:SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION
TLC320AD50CPT 功能描述:接口—CODEC SNGL CH Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLC320AD50CPTR 功能描述:接口—CODEC SNGL CH Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLC320AD50I 制造商:TI 制造商全稱:Texas Instruments 功能描述:SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION
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