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TDC2302B
STS-3/STM-1 LINE INTERFACE
SDNS002 – SEPTEMBER 1992 – REVISED JUNE 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
2
functional block diagram
RXSDT
RXSDC
Byte/
Nibble
RX
Output
TLB
RXSCT
RXSCC
HSCKT
HSCKC
Pseudo-
ECL/CMOS
Converters
8
5
8
RCK
R Data
Byte
Clock
Data
FLB
OOFN
MODE
Pseudo-ECL
155.52-Mbits/s
Input
Framing
Block
Receive
Mode/
Alarm
Block
Facility
Loopback
Terminal
Loopback
RXBDn
RXBC
RXRF
RXF
LOS, RFE,
LOF, OOF,
B1ERR
BSCRM
NIB
RESET
8
TXBDn
TXBC
TXF
TXRF
TXRC
Transmit
Mode
Block
Parallel/
Serial
Converter
CMOS/
Pseudo-ECL
Drivers
8
Data
Clock
HS
Byte
Clock
TXSDT
TXSDC
Byte/
Nibble
TX
Input
Reference
Clock and
Frame
Pseudo-ECL
155.52-Mbits/s
Output
HSCK
TXSCT
TXSCC
(TPINV)
description
The TDC2302B provides a complete frame synchronization function for a STS-3/STM-1 signal interface. The
device frame aligns the incoming 155.52-Mbits/s serial data stream and converts it to a byte or nibble data
output. A byte or nibble clock output is also provided along with a frame indication signal. In the transmit
direction, the TDC2302B accepts byte or nibble data and clock and outputs a 155.52-Mbits/s serial data stream.
The device can be programmed to provide signal descrambling/scrambling and B1 byte parity
checking/generation. The TDC2302B also monitors the incoming serial data and provides a loss of signal (LOS)
indicator. In addition, loopback of both the facility serial line input and the terminal byte/nibble input is provided.
The TDC2302B provides two modes of frame synchronization: tracking or nontracking. When the tracking mode
is activated, the device finds the frame of the incoming signal and monitors the signal continuously for frame
alignment errors. In this operating mode, outputs are provided to indicate a receive frame error (RFE),
out-of-frame error (OOF), or loss-of-frame error (LOF). If the nontracking mode is activated, the device finds
the frame of the incoming signal, but no subsequent monitoring of the signal is provided. In this mode, the RFE,
OOF, and LOF outputs are deactivated.
The serial data and clock inputs and outputs operate at pseudo-ECL levels (ECL levels referenced to 5 V instead
of 0 V). Of the remaining I/O signals, the inputs are TTL compatible, and the outputs are CMOS. The TDC2302B
is specified for operation over a temperature range of –40
°
C to 85
°
C.