參數(shù)資料
型號: TDC2302B
廠商: Texas Instruments, Inc.
英文描述: STS-3/STM-1 Line Interface(STS-3/STM-1線性接口)
中文描述: STS-3/STM-1線路接口(STS-3/STM-1線性接口)
文件頁數(shù): 15/17頁
文件大?。?/td> 390K
代理商: TDC2302B
TDC2302B
STS-3/STM-1 LINE INTERFACE
SDNS002 – SEPTEMBER 1992 – REVISED JUNE 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
15
timing requirements (see Figures 16 and 17) (continued)
MIN
MAX
UNIT
td(RXBD)
td(B1E)
Delay time, RXBD after RXBC
Delay time, B1ERR
after RXBC
0
6
ns
0
6
ns
td(B1E)
td(RXBD)
B1ERR
RXBDn
RXBC
Last Data Byte/Nibble
of the First Row of the
Payload
Bit Error
B1 Parity Bit 7
Bit O.K.
B1 Parity Bit 6
B1
MSB Nibble
B1
LSB Nibble
NOTE: Four time slots of B1ERR output are shown; up to eight bits may be in error in a given frame.
Figure 16. B1 Error Pulse Timing – Nibble Mode
MIN
NOM
MAX
UNIT
tw(TXSC)L
tw(TXSC)H
tc(TXSC)
tsu(TXSD)
th(TXSD)
Pulse duration, TXSC low
2.9
ns
Pulse duration, TXSC high
2.9
ns
Clock cycle time, TXSC
Setup time, TXSD before TXSC
Hold time, TXSD after TXSC
6.43
ns
1
ns
1.25
ns
TXSD
TXSC
tsu (TXBD)
th(TXBD)
tw(TXSC)H
tc(TXSC)
tw(TXSC)L
ìììì
ìììì
ìììì
ìììì
ìììì
ìììì
Figure 17. Line-Side PECL Output Timing
ìììì
ìììì
ìììì
ììììì
ììììì
ììììì
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