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參數(shù)資料
| 型號(hào)： | TFB2022AM |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Futurebus+ Data Path Unit(面向未來(lái)總線數(shù)據(jù)線單元) |
| 中文描述： | Futurebus數(shù)據(jù)路徑組（面向未來(lái)總線數(shù)據(jù)線單元） |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大?。?/td> | 122K |
| 代理商： | TFB2022AM |
TFB2022AM
FUTUREBUS+ DATA PATH UNIT
SGLS072A – JANUARY 1992 – REVISED MARCH 1994
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Parallel-Protocol Support Is Fully
Compliant to Futurebus+ Standard
(IEEE Std 896.1–1991)
Interfaces to a Variety of Popular
Microprocessors Such as SPARC
, 680x0,
88xxx, 80x86, and Alpha AXP
Can be Used in Conjuction With the
TFB2002BM or Standalone With a
User-Defined Controller
64 Data Channels and 8 Parity Channels on
Board
Supports 32 or 36 Bits of Addressing
Package is a Ceramic Quad Flat Package
With a 3-Inch Nonconductive Tie Bar,
Lead Pitch Is 0.5 mm (19.7 mil)
Can Handle a Single Outstanding Split
Transaction
On-Board Address Decoding Determines
Whether Transaction is to Host Memory,
Extended Unit Space, Message-Passing
Mailbox, or Other CSR Location
Parallel-Protocol-Related CSR Locations
Are Provided on Chip
Provides Support for Module Live Insertion
Handles Both Packet and Compelled
Transfers
Capable of Buffering up to 256 Bytes Per
Transaction
description
The TFB2022AM data-path unit (DPU) is a member of the Texas Instruments Futurebus+ chip set. This chip
set provides an integrated approach to the Futurebus+ interface that reduces new-product design time, allows
more functionality per circuit board, improves overall interface reliability, and reduces end-user down time
through built-in test capabilities.The Futurebus+ chip set is capable of supporting, in any combination, 32- or
64-bit data widths on both the host-bus interface and Futurebus+. The address width is programmable to be
32 bits or 36 bits (with either data width).
The TFB2022AM can be used with a TFB2002BM Futurebus+ I/O controller to provided a complete 64-bit
Profile B interface. It allows great flexibility in the design of the system and in the host features that can be
supported. It can also be used with a user-defined controller to provide a variety of performance features. When
used together, the TFB2022AM and TFB2002BM provide the Futurebus+ and host bus protocol control for the
first 64 bits of data and 36 bits of address. The TFB2022AM contains a bidirectional FIFO for high-speed
transmission of data in either compelled or packet mode, address control for 36 bits of address, and related CSR
locations. All Profile-A-/ and Profile-B-required CSRs are implemented either on this device the or TFB2002BM.
The TFB2022AM is optimized for Profile-B modules. Several processors can reside on a single module with
the DPU as long as they do not require the DPU/IOC to understand cache-coherent operation. The module can
contain memory or I/O units in addition to processors. The TFB2022AM is best suited for I/O or memory
modules.
The MS<1:0> signals provide a pre-address decode mechanism, enabling the user to implement simplified
decode logic in the logic interface. These signals indicate whether an access is being made to host memory,
extended units space, host CSR space or to a message mailbox.
The TFB2022AM is characterized over the full military temperature range of –55
°
C to 125
°
C
SPARC is a trademark of Sun Microsystems, Inc.
Alpha AXP is a trademark of Digital Equipment Corporation.
Copyright
1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
P
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