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參數(shù)資料
| 型號(hào)： | TDC2302B |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | STS-3/STM-1 Line Interface(STS-3/STM-1線性接口) |
| 中文描述： | STS-3/STM-1線路接口（STS-3/STM-1線性接口） |
| 文件頁(yè)數(shù)： | 13/17頁(yè) |
| 文件大小： | 390K |
| 代理商： | TDC2302B |
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TDC2302B
STS-3/STM-1 LINE INTERFACE
SDNS002 – SEPTEMBER 1992 – REVISED JUNE 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
13
timing requirements (see Figures 11, 12, and 13) (continued)
MIN
NOM
MAX
UNIT
tw(TXRF)2
tw(TXRC)H
tw(TXRC)L
tc(TXRC)
td(TXRF)
Pulse duration, TXRF
25.72
ns
Pulse duration, TXRC high
9
ns
Pulse duration, TXRC low
9
ns
Clock cycle time, TXRC
Delay time, TXRF
↑
after TXRC
↓
25.72
ns
0
6
ns
TXRC
tw(TXRC)H
tw(TXRC)L
tc(TXRC)
td(TXRF)
TXRF
tw(TXRF)2
Figure 11. Terminal-Side Nibble Reference Signals Output (TPINV high)
MIN
MAX
UNIT
td(OOF/LOF)
tw(OOFN)
Delay time, OOF/LOF after OOFN
↑
Pulse duration, OOFN
0
312
ns
105
ns
OOF/LOF
ììììììììììì
ììììììììììì
Figure 12. OOFN Resetting Frame
td(OOF/LOF)
tw(OOFN)
OOFN
Active High Only
MIN
MAX
UNIT
td(TXRC)R
td(TXRF)
tw(RESET)
Delay time, TXRC after RESET
↑
Delay time, TXRF
↓
after TXRC
↑
Pulse duration, RESET low
6
30
ns
0
6
ns
105
ns
TXRC
ìììììììììì
ìììììììììì
ìììììììììì
td(TXRC)R
RESET
td(TXRF)
TXRF
Figure 13. RESET Effect of Reference Clock and Frame (TPINV low)
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