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參數(shù)資料
| 型號： | TDA9106A |
| 廠商： | 意法半導體 |
| 英文描述： | LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| 中文描述： | 低成本多頻監(jiān)聽音箱偏轉處理器 |
| 文件頁數(shù)： | 7/30頁 |
| 文件大?。?/td> | 317K |
| 代理商： | TDA9106A |
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HORIZONTAL SECTION
(continued)
ElectricalCharacteristics
(V
CC
= 12V,T
amb
= 25
o
C) (continued)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
1st PLL SECTION
HpolT
V
VCO
Polarity Integration Delay
VCO Control Voltage (Pin12)
0.75
ms
V
REF-H
= 8V
0
f
H
(Max.)
R
= 6.49k
, C
0
= 820pF,
dF/dV = 1/11R
0
C
0
% of Horizontal Period
Sub-Address 01, Pin 14
Byte x1111111
Byte x1000000
Byte x0000000
R
0
= 6.49k
, C
0
= 820pF,
f
0
= 0.97/8R
0
C
0
V
REF-H
/ 6
17
V
V
Vcog
VCO Gain(Pin 12)
kHz/V
Hph
Horizontal Phase Adjustment
Horizontal Phase Decoupling Output
Minimum Value
Typical Value
Maximum Value
FreeRunning Frequency
±
10
%
Hphmin
Hphtyp
Hphmax
f
0
2.8
3.4
4.0
22.3
V
V
V
kHz
dF0/dT
FreeRunning Frequency Thermal Drift
(No drift on external components)
PLL1 Capture Range
-150
ppm/C
CR
R
= 6.49k
, C
= 820pF,
from f
+0.5kHz to 4.5F
0
f
H
(Min.)
f
H
(Max.)
Typ Threshold = 1.6V
PLL ON
PLL OFF
Sub-Address 02
100
23.5
kHz
kHz
PLLinh
PLL1 Inhibition (Pin3)
2
0.8
V
V
SFF
Safe Forced Frequency
SF1 Byte 11xxxxxx
SF2 Byte 10xxxxxx
VCO SawtoothLevel
High FC1=(4.V
REF-H
)/5
Low FC2=(V
REF-H
)/5
2F0
3F0
FC1
FC2
Pin 9 To filter
Pin 8 To filter
6.4
1.6
V
V
2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION
FBth
Hjit
FlybackInput Threshold Voltage (Pin 6)
Horizontal Jitter (see Pins8-9 filtering)
Horizontal Drive Output Duty-Cycle
(Pin 20 or 21) (see Note 1)
X-RAY Protection Input Threshold Voltage
Internal Clamping Levels on 2nd PLL Loop
Filter(Pin 4)
Threshold Voltage To Stop H-Out,V-Out
when V
CC
< VSCinh
Maximum Horizontal Blanking Output
Current
Horizontal Blanking Output Low Level
(Blanking ON)
Horizontal Drive Output
Low Level (Pin 20 to GND)
High Level (Pin 21 to V
CC
=12V)
0.65
0.75
TBD
48
V
ppm
%
XRAYth
Vphi2
Pin 15
Low Level
High Level
Pin 18
8
V
V
V
V
1.6
4.0
7.5
VSCinh
IHblk
I
22
10
mA
VHblk
V
22
with I
22
= 10mA
0.25
0.5
V
HDvd
HDem
V
21
-V
20
, I
OUT
= 20mA
V
20
, I
OUT
9.5
1.1
10
1.7
V
V
Notes :
1. Duty Cycle is theratio of power transistor OFF time to period. Power transistor is OFF when output transistor is OFF.
2. Initial Condition for Safe Operation Start Up (Max. duty cycle).
9
TDA9106A
7/30
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