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參數(shù)資料
| 型號： | TDA9106A |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| 中文描述： | 低成本多頻監(jiān)聽音箱偏轉(zhuǎn)處理器 |
| 文件頁數(shù)： | 20/30頁 |
| 文件大小： | 317K |
| 代理商： | TDA9106A |
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11
12
Loop
Filter
R0
1.6V
6.4V
10
C0
6.4V
1.6V
0 0.875T T
RS
FLIP FLOP
(1.3V < V
< 6V)
12
I
0
2
4 I
0
I
0
9
8
47nF
47nF
9
Figure 10 :
Detailsof VCO
LOCKDET
13
H-LOCKCAP
COMP1
SYNC
PROCESSOR
38
H/HVIN
High
CHARGE
PUMP
Low
PLL
INHIBITION
VCO
3
PLL1INHIB
12
11
10
PLL1F
R0
C0
PHASE
ADJUST
E2
14
H-POS
I
2
C
HPOS
Adj.
OSC
TRAMEXT
TRAMEXT SMFE *
LOCK/UNLOCK
STATUS
33
VSYNCIN
1
S/G
* SMFE : Safety FrequencyMode Enable
9
Figure 9 :
PLL1 Block Diagram
OPERATINGDESCRIPTION
(continued)
The control voltage of the VCO is typically com-
prisedbetween1.33Vand6V(seeFigure 10).The
theoricalfrequencyrange ofthisVCOis intheratio
1 to 4.5, the effective frequency range has to be
smaller 1 to 4.2 due to clamp interventionon filter
lowest value.
The synchro frequency has to be always higher
thanthe freerunningfrequency.Asan examplefor
a synchro range from 24kHz to 100kHz, the sug-
gested free running frequencyis 23kHz.
An other feature is the capability for MCU to force
horizontal frequency through I
2
C to 2xF0 or 3xF0
(for burn in mode or safety requirement).In this
case,inhibitionswitch is openedleavingPLL1free
butvoltageonPLL1filterisforcedto 2.66Vfor2xF0
or 4.0V for 3xF0.
The PLL1 ensures the coincidence between the
leading edge of the synchro signal and a phase
reference obtained by comparison between the
sawtooth of the VCO and an internal DC voltage
I
2
C adjustable between 2.8V and 4.0V (corre-
sponding to
±
10%) (see Figure 11). This voltage
has to be filteredon Pin14 so as to optimizejitter.
The TDA9106Aalso includes a Lock/Unlockiden-
tification block which senses in real time wheither
PLL1 is locked on the incoming horizontal sync
signalor not. The resultinginformationis available
on Hlockout (see Synchro Processor). The block
H Osc
Sawtooth
Phase REF1
H Synchro
1.6V
Vb
6.4V
2.8V<Vb<4.0V
7/8T
H
1/8T
H
PhaseREF1 is obtainedby comparisonbetween thesawtoothand
a DC voltage adjustable between 2.8V and 4.0V. The PLL1 en-
sures theexact coincidence between the signals phase REFand
HSYNS. A
±
T/10phase adjustment is possible.
9
Figure 11:
PLL1Timing Diagram
TDA9106A
20/30
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