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參數(shù)資料
| 型號(hào)： | TDA9106A |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| 中文描述： | 低成本多頻監(jiān)聽音箱偏轉(zhuǎn)處理器 |
| 文件頁數(shù)： | 18/30頁 |
| 文件大小： | 317K |
| 代理商： | TDA9106A |
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I.6 - Sync IdentificationStatus
TDA9106Ais ableto feedbackto theMCU(thanks
toI
2
C) theSyncinputstatus(syncidentification)so
thattheMCUcan chooseSyncprioritythroughI
2
C.
AsextractedVerticalsyncpulseis performedwhen
choicealreadyoccuredand when 12Vis supplied,
werecommendto usethedeviceas following:(that
means thateven in Powermanagementmode the
IC is able to inform MCU on detected synchro
signalsdue to its 5V supply).
First,refreshSynchrodetectionbyI
2
C.Thencheck
the status of H/V det and Vdet by I
2
C read.
Sync priority choice shouldbe :
Table1 :
Sync Priority Choice
H/V det
V det
Sync priority
Subaddress 03
D8
1
0
Comment
D7
1
1
Synchro type
Separated H & V
Composite TTL
H&V
Sync on Green
Yes
Yes
Yes
No
No
No
0
0
Of course, when choice is done, one can refresh
the synchro detections and verify that extracted
Vsync is present and thatno synchro type change
occured.
Synchro processor is also giving synchro polarity
information.
I.7 - IC status
TheICcaninformtheMCUeitherthe1stHorizontal
PLLor Verticalsectionare lockedornot, andif Xray
has been activated.
This last status permits to the MCU :
- reset the Xray internal latch decreasing the V
CC
supply
- directly reset throwthe I
2
C interface.
OPERATINGDESCRIPTION
(continued)
I.8 - SynchroInputs
Both H/HVin and Vsyncin inputs are TTL compat-
ibletriggerwithHysterisistoavoiderraticdetection.
It includes pull up resistorto V
DD
.
Vertical sync extractor is included for composite
syncorcompositevideo.Applicationengineermust
adapt resistor R and capacitor C dedicated to its
application.
1
S/G
R
C
1k
I
(Typ.)
= 10
μ
A
1.6V
TDA9106
9
Figure 5
ResistorR isfixedby detectionthreshold wanted:
R < (V
THRESHOLD
/ I
REF
)
Then C is determinedby maximum pulse width to
detect(in general,vertical sync width) :
RC > (maxpulse width)
I.9 - SynchroProcessorOutputs
Synchro processor delivers on 3 TTL-compatible
CMOS outputsthe followingsignals :
- Hout as follow :
Sync Mode
Separated
TTL Composite
S/G
- Vsyncout is either vertical extracted pulseoutput
or Vsyncininput. It keeps the input polarity.
- HlockoutistheHorizontal1stPLLstatus:0Vwhen
locked. It permits MCU to adjust free running
frequencyand optimizesthe IC performance.
Hout Mode
Horizontal
TTL Composite
Composite
Hout Polarity
Same as Input
Same as Input
Negative
TDA9106A
18/30
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