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參數(shù)資料
| 型號： | TDA9106A |
| 廠商： | 意法半導體 |
| 英文描述： | LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| 中文描述： | 低成本多頻監(jiān)聽音箱偏轉(zhuǎn)處理器 |
| 文件頁數(shù)： | 26/30頁 |
| 文件大?。?/td> | 317K |
| 代理商： | TDA9106A |
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Thevertical partgeneratesa fixedamplituderamp
whichcanbe affectedby SandCcorrectionshape.
Then,theamplitudeof thisrampisadjustedto drive
an externalpower stage (see Figure22).
Theinternal referencevoltageusedforthe vertical
part is available between Pin 26 and Pin 24. Its
typical value is :
V
26
= V
REF
= 8V
The charge of the external capacitor on Pin 27
(VCAP)generatesafixedamplituderampbetween
theinternalvoltages,V
l
(V
l
= V
REF
/4) andV
H
(V
H
=
5/8 x V
REF
).
When the synchronizationpulse is not present,an
internal current source sets the free running fre-
quency.For an external capacitor, C
OSC
= 150nF,
the typical free running frequencyis 106Hz.
Typical free running frequency can be calculated
by :
f
0
(
Hz
)
=
1.6 e
5
1
C
OSC
A negative or positive TTL level pulse applied on
Pin33 (VSYNC) as well as a TTL composite sync
on Pin 38 or a Sync on Green signal on Pin 1 can
synchronise the ramp in the range [fmin , fmax].
This frequency range depends on the external
capacitor connected on Pin 27. A capacitor in the
range [150nF, 220nF]
±
5% is recommanded for
applicationin thefollowingrange: 50Hzto 120Hz.
Typicalmaximumand minimumfrequency,at25
o
C
and without any correction (S correction or C cor-
rection),can be calculatedby :
f
(Max.)
= 2.5 x f
0
and f
(Min.)
= 0.33 x f
0
If S or C corrections are applied, these values are
slighty affected.
If a synchronization pulse is applied, the internal
oscillator isautomaticalysynchronizedbutthe am-
plitude is no more constant.An internalcorrection
is activatedto adjustit in less than a half a second
: the highestpoint of the ramp (Pin 27) is sampled
on the sampling capacitor connectedon Pin 25 at
eachclockpulse andatransconductanceamplifier
generatesthe chargecurrent of the capacitor.The
ramp amplitude becomes again constant and fre-
quencyindependant.
The read statusregisterenables to havethe verti-
cal Lock-Unlock and the vertical Sync Polarity in-
formations.
It isrecommandedto usea AGCcapacitorwithlow
leakagecurrent.Avalue lower than100nAis man-
datory.
Goodstabilityof theinternalclosedloopis reached
bya470nF
±
5%capacitorvalueon Pin25 (VAGC).
Pin 30, VFLY is the vertical flyback input used to
generate the vertical blanking signal on Pin 23. If
Vfly is not used,(V
REF
- 0.5),at minimum, mustbe
connectedto this input.
In such case, the vertical blanking output will be
activated by the vertical sync input signal and re-
setted by the end of vertical sawtooth discharging
pulse.
III.6 - I
2
C Control Adjustments
Then, S and C correctionshapescan be added to
this ramp. This frequency independent S and C
corrections are generated internally. Their ampli-
tudeareadjustablebytheirrespectiveI
2
C register.
They can also be inhibitedby their Selectbit.
At the end, theamplitudeof thisS and C corrected
ramp can be adjusted by the vertical ramp ampli-
tude control register.
The adjustedramp is availableon Pin29 (V
OUT
) to
drive an external power stage.
The gain of this stage is typically 25%depending
on its registervalue.
The DC value of this ramp is kept constant in the
frequency range, for any correction applied on it.
its typical value is V
MID
= 7/16
V
REF
.
A DC voltage is available on Pin 28 (VDCOUT). It
is driven by its own I
2
C register(vertical Position).
Its value is V
DCOUT
= 7/16
V
REF
±
300mV.
So theV
DCOUT
voltageis correlatedwith DCvalue
of V
OUT
. It increasesthe accuracy when tempera-
ture varies.
III.7 - Basic Equations
In firstapproximation,the amplitudeof therampon
Pin 29 (Vout)is :
V
OUT
- V
MID
= (V
OSC
- V
MID
)
(1 + 0.25(V
AMP
))
with V
MID
= 7/16
V
REF
; typically 3.5V,the middle
value of the ramp on Pin 27
V
OSC
= V
27
, rampwith fixed amplitude
V
AMP
is -1 for minimum vertical amplitude register
OPERATINGDESCRIPTION
(continued)
TDA9106A
26/30
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