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參數(shù)資料
| 型號： | TDA9106A |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| 中文描述： | 低成本多頻監(jiān)聽音箱偏轉(zhuǎn)處理器 |
| 文件頁數(shù)： | 19/30頁 |
| 文件大小： | 317K |
| 代理商： | TDA9106A |
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II - HORIZONTAL PART
II.1 - Internal Input Conditions
Horizontalpart isinternallyfed by synchroproces-
sorwithadigitalsignal.correspondingtohorizontal
synchropulses or to TTLcompositeinput.
Concerning the duty cycle of the input signal, the
following signals (positive or negative) may be
appliedto the circuit.
Using internal integration, both signals are recog-
nizedonconditionthatZ/T<25%.Synchronization
occurs on the leading edge of the internal sync
signal.The minimum value of Z is 0.7
μ
s.
OPERATINGDESCRIPTION
(continued)
9
Figure 6
Another integrationis able to extractverticalpulse
ofcompositesynchroifdutycycleismorethan25%
(typicallyd = 35%).
d
d
C
TRAMEXT
9
Figure 7
The last feature performed is the equalizing pulses
removingtoavoidparasiticpulsesonphasecompara-
torinputwhichisintolerenttowrongormissingpulse.
II.2 - PLL1
The PLL1 is composed of a phase comparator, an
externalfilterandavoltagecontrolledoscillator(VCO).
Thephasecomparatoris a“phasefrequency”type
designed in CMOStechnology.This kind of phase
detector avoids locking on false frequencies.It is
followed by a “charge pump”, composed of two
current sources sunk and sourced (I = 1mA Typ.
when locked, I = 140
μ
A when unlocked). This
difference between lock/unlock permits a smooth
catching of horizontal frequency by PLL1. This
effectisreinforcedbyaninternaloriginalslowdown
system when PLL1 is locked avoiding Horizontal
too fast frequencychange.
The dynamic behaviour of the PLL is fixed by an
external filter which integrates the current of the
chargepump.A“CRC”filteris generallyused (see
Figure 8).
PLL1isinternallyinhibitedduringextractedvertical
sync (if any) to avoid taking in account missing
pulses or wrong pulses on phase comparator.The
inhibition results from the opening of a switch lo-
catedbetweenthe chargepumpand the filter(see
Figure 9). For particular synchro type, MCU can
drive Pin 3 to high level (TTL compatible input) to
inhibit PLL1. It can also be used to avoid PLL1
locking on synchroinputsif a“dangerous”mode is
detectedby the MCU.
TheVCOusesan externalRC network.It deliversa
linearsawtoothobtainedbychargeanddischargeof
the capacitor, by a current proportionnalto the cur-
rentintheresistor.Typicalthresholdsofsawtoothare
1.6Vand6.4V.Thesetwolevelsareaccessibletobe
filteredason Figure 10to improve jitter.
12
PLL1F
9
Figure 8
TDA9106A
19/30
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