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參數資料
| 型號： | TDA9103 |
| 廠商： | 意法半導體 |
| 英文描述： | Deflection Processor for Multisync Monitor(用于多路同步監(jiān)控器的偏轉處理器) |
| 中文描述： | 偏轉處理器的多頻顯示器（用于多路同步監(jiān)控器的偏轉處理器） |
| 文件頁數： | 18/27頁 |
| 文件大?。?/td> | 305K |
| 代理商： | TDA9103 |
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Function
When the synchronisationpulse is not present, an
internal current source sets the free running fre-
quency. For an external capacitor,C
OSC
= 180nF,
the typicalfree running frequencyis 84Hz.
Typical free running frequency can be calculated
by :
f
0
(
Hz
) =
1.5
10
5
1
C
OSC
(
nF
)
A negative or positive TTL level pulse applied on
Pin 34 (VSYNC) can synchronise the ramp in the
frequencyrange [fmin, fmax].This frequencyrange
dependsontheexternalcapacitorconnectedonPin
27. A capacitor in the range [150nF, 220nF] is re-
commanded for application in the following
range: 50Hzto 120Hz.
Typical maximum andminimum frequency,at 25
°
C
and without any correction (S correction or C cor-
rection), can be calculated by :
f
max
= 2.5
f
0
f
min
= 0.33
f
0
If S or C corrections are applied,these values are
slighty affected.
If an externalsynchronisation pulse is applied, the
internal oscillator is automaticaly caught but the
amplitude is no more constant. An internalcorrec-
tion is activated to adjust it in less than half a
second: the highest voltageof the ramp on Pin27
is sampledonthesamplingcapacitorconnectedon
Pin 25 (VAGCCAP) at each clock pulse and a
transconductanceamplifier generates the charge
current of the capacitor. The ramp amplitude be-
comes again constant.
Itis recommandedto usea AGCcapacitorwithlow
leakage current. Avaluelower than100nAis man-
datory.
DC Control Adjustments
Then, a S correction shape can be added to this
ramp. This frequencyindependentS correction is
generatedinternally;its amplitudeisDCadjustable
on Pin28 (V
SAMP
) andit can be centered to gener-
ate C correction, according to the voltage applied
on Pin 29 (V
SCENT
).
It is non effectivefor V
SAMP
lower than V
REF
/4 and
maximum for V
SAMP
= 3/4
V
REF
.
Endly, the amplitude of this S corrected ramp can
be adjusted by the voltage applied on Pin 31
(V
AMP
). The adjusted ramp is available on Pin 30
(V
OUT
) to drive an externalpower stage. The gain
of thisstageistypically
±
30%whenvoltage applied
on Pin31 is in the range V
REF
/4 to 3/4
V
REF
. The
DC value of this ramp is kept constant in the
frequency range , for any correction applied on it.
Its typicalvalue is :
V
DCOUT
= V
MID
= 7/16
V
REF
.
ADC voltage is available on Pin 32 (V
DCOUT
). Itis
driven bythe voltageapplied onPin 33 (V
POS
). For
a voltage control range between V
REF
/4 and 3/4
V
REF
, the voltage available on Pin 32 is :
V
DCOUT
= 7/16
V
REF
±
300mV.
So, theV
DCOUT
voltageis correlated withDCvalue
of V
OUT
. It increases the accuracywhen tempera-
ture varies.
Basic Equations
In firstapproximation,theamplitude of theramp on
Pin 30 (V
OUT
) is :
V
OUT
- V
MID
= (V
CAP
- V
MID
) [1 + 0.16
(V
AMP
- V
REF
/2)]
with V
MID
= 7/16
V
REF
; typically 3.5V
V
MID
isthemiddlevalueof therampon Pin27
V
CAP
= V
27
, ramp with fixed amplitude.
On Pin32 (V
DCOUT
), the voltage (in volts) is calcu-
lated by :
V
DCOUT
=V
MID
+ 0.16
(V
POS
- V
REF
/2).
V
POS
is the voltageappliedon Pin33.
The center of the S correctioncan be approxima-
tively calculated according to the voltage applied
on Pin29 (V
SCENT
) :
V
CENTER
= V
MID
+ 0.25
(V
SCENT
- V
REF
/2)
This is an internal voltage used to adjust the C
correction. The S correction can be adjusted along
the ramp according to this parameter.It is ineffec-
tive when VSAMPis lower than VREF/4.
The current available on Pin 27
(when V
SAMP
= V
REF
/4) is :
I
OSC
= 3/8
V
REF
C
OSC
f
C
OSC
: capacitorconnectedon Pin27
f synchronisationfrequency
The recommanded capacitor value on Pin 25
(V
AGC
) is470nF.Its assumesa goodstabilityofthe
internal closed loop.
TDA9103
18/27
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