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參數(shù)資料
| 型號(hào)： | TDA9103 |
| 廠(chǎng)商： | 意法半導(dǎo)體 |
| 英文描述： | Deflection Processor for Multisync Monitor(用于多路同步監(jiān)控器的偏轉(zhuǎn)處理器) |
| 中文描述： | 偏轉(zhuǎn)處理器的多頻顯示器（用于多路同步監(jiān)控器的偏轉(zhuǎn)處理器） |
| 文件頁(yè)數(shù)： | 11/27頁(yè) |
| 文件大?。?/td> | 305K |
| 代理商： | TDA9103 |
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V
REF
10k
22k
DC Control Voltage
10k
9
Figure 5 :
Example of Practical DC Control
Voltage Generation
Z
T
Z
9
Figure 6
1.6V
HSYNC
9
Figure 7 :
Input Structure
OPERATINGDESCRIPTION
GENERAL CONSIDERATIONS
Power Supply
The typicalvalue of the power supply voltage V
CC
is 12V.Perfectoperationis obtainedif V
CC
ismain-
tained in the limits : 10.8V
→
13.2V.
In order to avoid erratic operation of the circuit
during the transientphase of V
CC
switchingon, or
switching off, thevalue ofV
CC
ismonitoredandthe
outputs of the circuit are inhibited if it is too low.
In ordertohaveaverygoodpowersupplyrejection,
the circuitis internally poweredby severalinternal
voltage references (The unique typical value of
which is 8V). Two of these voltage referencesare
externallyaccessible, one for the verticalpart and
one for the horizontal part. These voltage refer-
ences can be used for the DC control voltages
applied onthe concernedpinsby the wayof poten-
tiometers or digital to analog converters (DAC’s).
Furthermoreit is possible to filterthe a.m. voltage
references by the use of external capacitor con-
nected to ground, in order to minimize the noise
and consequentlythe ”jitter” on vertical and hori-
zontal output signals.
DC Control Adjustments
The circuithas10adjustmentcapabilities:3forthe
horizontal part, 1 for the SMPS part, 2for the E/W
correction,4 forthe vertical part.
The corresponding inputs of the circuit has to be
driven with a DC voltage typically comprised be-
tween 2 and 6V for a value of the internal voltage
referenceof 8V.
More precisely, the control voltages have to be
maintained between V
REF
/4 and 3/4
V
REF
. The
application of controlvoltages outsidethisrangeis
not dangerousforthecircuitbutthegoodoperation
is not guaranted (except for Pin 2 : duty cycle
adjusment. See outputsinhibitionparagraph).
The input currents of the DC control inputs are
typicallyvery low (about a few
μ
A). Depending on
the internal structure of the inputs, the input cur-
rents can be positiveor negative(sink or source).
HORIZONTAL PART
Input section
The horizontal input is designed to be sensitiveto
TTLsignalstypically comprised between0and 5V.
The typicalthresholdof thisinputis1.6V.Thisinput
stage uses an NPN differentialstage and the input
current is very low.
Concerning the duty cycle of the input signal, the
following signals may beapplied to the circuit.
Using internal integration, both signals are recog-
nizedonconditionthatZ/T
≤
25%. Synchronisation
occurs on the leading edge of the rectified signal.
The minimum value of Z is 0.7
μ
s.
PLL1
The PLL1is composedof a phasecomparator,an
external filter and a Voltage Controlled Oscillator
(VCO).
Thephasecomparatorisa”phasefrequency”type,
designedin CMOS technology.This kind of phase
detector avoids locking on false frequencies. It is
followed by a ”charge pump”, composed of 2 cur-
rent sourcessink and source(I = 1mAtyp.)
TDA9103
11/27
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