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參數(shù)資料
| 型號(hào)： | TDA9103 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Deflection Processor for Multisync Monitor(用于多路同步監(jiān)控器的偏轉(zhuǎn)處理器) |
| 中文描述： | 偏轉(zhuǎn)處理器的多頻顯示器（用于多路同步監(jiān)控器的偏轉(zhuǎn)處理器） |
| 文件頁數(shù)： | 12/27頁 |
| 文件大?。?/td> | 305K |
| 代理商： | TDA9103 |
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The dynamic behaviour of the PLL is fixed by an
external filter which integrates the current of the
charge pump. A ”CRC” filter is generallyused.
PLL1 is inhibited by applying a high level on Pin 35
(PLLinhib)whichisaTTLcompatibleinput.Theinhibi-
tion results from the openingof a switch located be-
tweenthechargepumpandthefilter (see Figure8).
The VCOuses an externalRC network. It delivers
a linear sawtooth obtained by charge and dis-
charge of the capacitor, bya current proportionnal
to the current in the resistor. typical thresholds of
sawtooth are 1.6Vand 6.4V.
12
PLL1F
9
Figure9
C Lockdet
13
LOCKDET
COMP1
INPUT
INTERFACE
CHARGE
PUMP
PLL
INHIBITION
Horizontal
Adjust
15
VCO
PHASE
ADJUST
Eini
35
R0 C0
11 10
Filter
12
Horizontal
Input
High
Low
E2
3.2V
OSC
17
9
Figure 8 :
Principle Diagram
The control voltage of the VCO is typically com-
prised between 1.6V and 6V. The theoretical fre-
quencyrange of this VCO is in the ratio 1
→
3.75,
but due to spread and thermal drift of external
componentsand the circuit itself, the effective fre-
quency range has to be smaller (e.g. 30kHz
→
82kHz).Intheabsenceofsynchronisationsignalthe
control voltage is equal to 1.6V typ. and the VCO
oscillates on its lowest frequency(free frequency).
Thesynchrofrequencyhastobealwayshigherthan
thefree frequencyandamarginhasto betaken.As
an example for a synchro range from 30kHz to
82kHz, the suggestedfree frequencyis 27kHz. To
compensatefor the spreadof externalcomponents
and of the circuit itself, the free frequencymay be
adjusted by a DC voltage on Pin 14 (Fmin adjust)
(see Figure10 fordetails).
The PLL1 ensures the coincidence between the
leading edge of the synchro signal and a phase
reference obtained by comparison between the
sawtooth of the VCO and an internal DC voltage
adjustablebetween 2.4V and 4V (by Pin 15). So a
±
45
°
phase adjustment is possible.
11
12
14
Loop
Filter
R0
(0.8V < a< 1.2V)
FHMINADJ
1.6V
6.4V
10
C0
6.4V
1.6V
0
0.75T T
RS
FLIP FLOP
a
(1.6V < V
< 6V)
12
I
0
I
0
2
4 I
0
2
9
Figure 10 :
Detailsof VCO and Fhmin Adjustment
TDA9103
12/27
相關(guān)PDF資料 |
PDF描述 |
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| TDA9105A | DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| TDA9105 | Deflection Processor for Multisync Monitors(偏轉(zhuǎn)處理器) |
| TDA9106A | LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TDA9105 | 制造商:Panasonic Industrial Company 功能描述:IC |
| TDA9105A | 制造商:Panasonic Industrial Company 功能描述:IC |
| TDA9106 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| TDA9106A | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| TDA9108 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MONITOR HORIZONTAL PROCESSOR |
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