參數(shù)資料
型號: TDA9103
廠商: 意法半導體
英文描述: Deflection Processor for Multisync Monitor(用于多路同步監(jiān)控器的偏轉處理器)
中文描述: 偏轉處理器的多頻顯示器(用于多路同步監(jiān)控器的偏轉處理器)
文件頁數(shù): 14/27頁
文件大?。?/td> 305K
代理商: TDA9103
C Lockdet
13
LOCKDET
COMP1
INPUT
INTERFACE
CHARGE
PUMP
PLL
INHIBITION
Horizontal
Adjust
15
VCO
PHASE
ADJUST
Eini
35
R0 C0
11 10
Filter
12
Freq
Adjust
High
Low
E2
3.2V
OSC
FAJUST
HFREQ
GENPULSE
COMP2
CHARGE
PUMP
High
Low
RAP
CYC
E2
E1
Adjust
Rapcyc
2
Cap
PH12
1
PWM
LOGI
PWM
BUFFER
FLYBACK
SortCOLL
Flyback
SortEM
VB
VA
Horizontal
Input
17
14
3
21
20
9
Figure 14 :
DualPLL Block Diagram
PLL2
The PLL2 ensures the coincidence between the
leading edge of the shaped flyback signal and a
phase referencesignal obtained bycomparison of
the sawtoothoftheVCOandaconstantDCvoltage
(3.2V) (see Figure 15).
The phasecomparatorof PLL2is similar to the one
of PLL1, it is followed by a charge pump with a
20k
400
Q1
GND 0V
3
HFLY
9
Figure 16 :
Flyback Input Electrical Diagram
H Osc
Sawtooth
Phase REF2
H Drive
1.6V
3.2V
6.4V
0.75T
0.25T
Ts
Duty Cycle
Shapped
Flyback
Flyback
9
Phase REF2is obtainedbycomparison betweenthe sawtoothand
a 3.2V (constant). The PLL2 ensures the exact
between the signals phase REF2 andthe flyback sigcoincidence
cycle of H-drive is adjustable between 30% and 50%.
Figure 15 :
PLL2Timing Diagram
±
0.5mA(typ.) output current.
TheflybackinputiscomposedofanNPNtransistor.
Thisinput has to be currentdriven. The maximum
recommanded input current is 2mA (see Fig-
ure 16).
Output Section
The H-drive signal is transmitted to the output
through a shaping block ensuring a duty cycle
adjustable from 30% to 50%. In order to ensure a
reliable operation of the scanning power part, the
output is inhibited in the following circumstances :
- V
CC
toolow.
- Xrayprotectionactivated.
- During the flyback.
- Outputvoluntarilyinhibited.
The outputstageis composedofa DarlingtonNPN
bipolartransistor.Boththecollectorandthe emitter
are accessible.
TDA9103
14/27
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