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參數(shù)資料
| 型號(hào)： | TDA9103 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Deflection Processor for Multisync Monitor(用于多路同步監(jiān)控器的偏轉(zhuǎn)處理器) |
| 中文描述： | 偏轉(zhuǎn)處理器的多頻顯示器（用于多路同步監(jiān)控器的偏轉(zhuǎn)處理器） |
| 文件頁(yè)數(shù)： | 13/27頁(yè) |
| 文件大?。?/td> | 305K |
| 代理商： | TDA9103 |
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SMPS Output
Inhibition
-
+
V
CC
30
REF 30
XRAY 30
V
CCoff
30
S
R
Q
-
+
H-duty Cycle 30
1V 30
-
+
Flyback 30
0.7V 30
30
PLL-Unloocked
V
CC
Checking
XRAYProtection
Inhibition
H Output
Inhibition
V Output
Inhibition
Blanking
9
Figure11 :
Safety FunctionsBlock Diagram
20k
220nF
13
From
Phase
Comparator
NOR1
A
6.5V
B
NOR2
23 SBLK OUT
H-Lock CAP
9
Figure 12 :
LOCK/UNLOCK Block Diagram
The TDA9103 also includes a LOCK/UNLOCK
identification block which sense in real-time
wheather the PLL is locked on the incomming
horizontalsyncsignalornot.Theresulting informa-
tion is available on safetyblanking output (Pin 23)
where it is mixedwith others information(see Fig-
ure 11). The block diagramof the LOCK/UNLOCK
function is described in Figure 12.
The NOR1 gateis receiving the phasecomparator
output pulses(which alsodrivesthechargepump).
When the PLL is locked,on point
A
thereis avery
small negative pulse (100ns) at each horizontal
cycle,so after R-C filter, thereisa highlevelon Pin
13 whichforce SBLK to high level (provided other
inputs on NOR2 are alsoat low level).
When the PLL is unlocked, the 100ns negative
pulseon
A
becomesmuchlargerandconsequently
the averagelevel on Pin 13 will decrease. When it
reaches 6.5V, point
B
goes to high level forcing
NOR2 open collector output to ”0”.
The statusof Pin13 is approximatelythe following :
- Near 0V when there is no H-SYNC,
- Between0 and4V with H-SYNC frequencydiffer-
H Osc
Sawtooth
Phase REF1
H Synchro
1.6V
Vb
6.4V
2.4V<Vb<4V
0.75T
0.25T
Phase REF1 is obtained by comparison between the sawtooth
and a DC voltage adjustable between 2.4V and 4V. The PLL1
ensures the exact coincidence between the signals phase REF
and HSYNS. A
±
45
°
phase adjustment ispossible.
9
Figure 13 :
PLL1 Timing Diagram
ent fromVCO,
- Between4 and 8V whenH-SYNC frequency
= VCO frequencybut not inphase,
- Near to 8V when PLL is locked.
It is important to noticethat Pin 13 is not an output
pinandmustonlybeusedforfilteringpurpose(see
Figure 12).
TDA9103
13/27
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| TDA9105A | DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| TDA9105 | Deflection Processor for Multisync Monitors(偏轉(zhuǎn)處理器) |
| TDA9106A | LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| TDA9106 | LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| TDE1737 | Interface Circuit - Relay and Lamp-Driver(接口電路(單片放大器驅(qū)動(dòng)繼電器和電子管)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TDA9105 | 制造商:Panasonic Industrial Company 功能描述:IC |
| TDA9105A | 制造商:Panasonic Industrial Company 功能描述:IC |
| TDA9106 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| TDA9106A | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| TDA9108 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:MONITOR HORIZONTAL PROCESSOR |
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