參數(shù)資料
型號： TDA8030
廠商： NXP Semiconductors N.V.
英文描述： USB smart card reader (OTP or ROM)
中文描述： USB智能卡閱讀器（OTP或光盤）
文件頁數(shù)： 34/57頁
文件大?。?/td> 228K
代理商： TDA8030
2003 Jul 04
34
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
8.4
MICROCONTROLLER
The embedded microcontroller is an 80C51RB+ with an
internal 16 kbyte EPROM (80C51FB with 16 kbyte ROM
for the TDA8031), 256 RAM and 512 AUXRAM. It has the
same instruction set as the 80C51.
Theembeddedmicrocontrollerisclockedbythefrequency
present on pin XTAL1.
The embedded microcontroller may be reset by an active
HIGH signal on pin RESET, but it is also reset by the
Power-on reset signal generated by the voltage
supervisor.
The external interrupt INT0 is used by the ISO UART, by
the analog drivers and by the ETU counters. It must be left
open-circuit in the application.
The external interrupt INT1 is used by the USB interface.
It must be left open-circuit in the application.
A general description, together with the added features, is
described below.
The added features to the 80C51 microcontroller are
similar to the 8XC51FB/RB+ microcontrollers, except for
the wake-up from power-down mode, which is enabled by
a falling edge on pin INT0 (card reader event) or on pin
INT1 due to the addition of an extra delay counter and
enable configuration bits within the UCR2 register; see
Section 8.4.1. For further information please refer to the
published specification of the 8xC51RB + /FB in “Data
Handbook IC20; 80C51-Based 8-bit Microcontrollers”
The 80C51 microcontroller has four 8-bit I/O ports, three
16-bit timer/event counters, a multi-source, 4-level priority
nestedinterruptstructure,anenhancedUARTandon-chip
oscillator and timing circuits. For systems that require
extra memory capability up to 64 kbytes, it can be
expanded by using standard TTL compatible memories
and logic.
1.
80C51 Central Processing Unit (CPU)
2.
Full static operation
3.
Security bits: ROM 2 bits
4.
Encryption array of 64 bits
5.
4-level priority structure
6.
6 interrupt sources
7.
Full duplex enhanced UART with framing error
detection and automatic address recognition
8.
Power control modes (the clock can be stopped and
resumed in IDLE mode and power-down mode)
9.
Wake-up from power-down by a falling edge on pins
INT0 and INT1; with an embedded delay counter
10. Programmable clock output
11. Second DPTR register
12. Asynchronous port reset
13. Low EMI (inhibit ALE).
Table 28 gives a list of main features to get a better
understanding of the differences between a standard
80C51, an 8XC51RB+ and the embedded microcontroller
in the TDA8030; TDA8031.
Table 28
Principal blocks in the 80C51, 8XC51RB+ and the TDA8030; TDA8031
FEATURE
80C51
8XC51RB+
TDA8030; TDA8031
ROM/EPROM
RAM
ERAM (MOVX)
PCA
WDT
T0
T1
T2
4 kbytes
128 bytes
no
no
no
yes
yes
no
16 kbytes
256 bytes
256 bytes
yes
yes
yes
yes
yes
lowest interrupt priority vector at 002BH
yes
yes
no
16 kbytes
256 bytes
512 bytes
no
no
yes
yes
yes
4 level priority interrupt
enhanced UART
delay counter
no
no
no
yes
yes
yes
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