參數資料
型號: TDA8030
廠商: NXP Semiconductors N.V.
英文描述: USB smart card reader (OTP or ROM)
中文描述: USB智能卡閱讀器(OTP或光盤)
文件頁數: 26/57頁
文件大?。?/td> 228K
代理商: TDA8030
2003 Jul 04
26
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
Table 24
Description of the CCR bits
Table 25
CLK value for an asynchronous card
Note
1.
If f
CLK
= f
XTAL
, the duty cycle must be ensured by the incoming clock signal on XTAL1.
BIT
SYMBOL
SHL
DESCRIPTION
7
6
5
not used
not used
Stop HIGH or LOW: If bit CST = 1, then the clock is stopped at LOW level if SHL = 0
and at HIGH level if SHL = 1. In these modes, the bias current in the card drivers is
reduced; the current drawn by the card (I
CC
) should be less than 10 mA at all V
CC
voltages.
Clock stop: In case of asynchronous cards, bit CST defines whether the clock to the
card is stopped or not. If bit CST is reset, then the clock is determined by bits AC0,
AC1 and AC2; see Table 25. All frequency changes are synchronous, thus ensuring
that no spike or unwanted pulse widths occurs during changes.
Synchronous Clock: In the event of synchronous cards, the clock contact is a copy of
the value written in SC. In reception mode, the data from the card is available in bit UR0
after a read operation of the URR register. In transmission mode, bit UT0 is written on
the I/O line of the card when UTR register has been written.
When switching from
1
n
f
xtal
to
1
2
f
int
or vice versa, only bit AC2 must be changed;
AC1 and AC0 must remain the same. When switching from
1
n
f
xtal
or
1
2
f
int
to CLK STOP
or vice versa, only bits CST and SHL must be changed.
When switching from
1
n
f
xtal
to
1
2
f
int
or vice versa, a maximum delay of 200
μ
s can occur
between the command and the effective frequency change on pin CLK. The fastest
switch is from
1
2
f
xtal
to
1
2
f
int
or vice versa, the best duty cycle is from
1
8
f
xtal
to
1
2
f
int
or
vice versa. The status bit CLKSW within the MSR gives the effective switch moment.
4
CST
3
SC
2 to 0
AC2 to AC0
AC2
AC1
AC0
CLK
(1)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
f
xtal
1
2
f
xtal
1
4
f
xtal
1
8
f
xtal
1
2
f
int
1
2
f
int
1
2
f
int
1
2
f
int
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