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TC9325F
2002-05-14
7
Pin No.
Symbol
Pin Name
Function and Operation
Remarks
67
HOLD
Hold mode control
input
Input pin for requesting and releasing
Hold mode.
Normally used to input radio mode
selection or battery detection signals.
Hold mode includes Clock Stop mode
(crystal oscillator stopped) and Wait
mode (CPU stopped), which can be
set by the CKSTP and WAIT
instructions respectively.
Clock Stop mode can be entered by
software in one of two ways: forcibly
or when Low level is detected on the
HOLD
pin. Clock Stop mode can be
released when High level is detected
on the
HOLD
pin or when the input
changes. Executing the CKSTP
instruction stops the clock generator
and CPU, entering memory backup
mode. In this state the device is set to
low current dissipation (10
μ
A max).
Wait mode is executed, regardless of
the
HOLD
pin input state, and the
device is set to low current
dissipation. To set wait mode, specify
by software either crystal oscillator
only operating or CPU suspended.
Wait mode is released when the
HOLD
pin input changes.
68
69
INTR1
INTR2
/PCTRin
External interrupt
input
/pulse count input
External interrupt input pins.
Enabling the interrupt function and
inputting a pulse (of at least 1.11 to
3.33
μ
s when the 4.5 MHz clock is in
use, or at least 13.3 to 40
μ
s when the
75 kHz clock used) to these input pins
generates an interrupt (INTR1/2) and
jumps the program to address 1/2.
The input logic and the clock edge
(rising/falling) can be individually
selected for each interrupt input.
The internal 8-bit timer clock can be
selected as input to the pins. At the
pulse count or when the count
reaches a specified value, an interrupt
can be generated (to address 5).
These pins are also used to input an
8-bit pulse counter. This counter can
be selected between rising and falling
edge input and between an
up-counter and a down-counter.
These pins are Schmitt inputs and can
also be used as input ports. The pins
can also be utilized as ports for
inputting remote control signals or
tape counts.
V
DD
V
DD