
TC9325F
2002-05-14
20
Machine Language (16 bits)
A
(2 bits)
Inst-
ruction
Set
Mnemonic
Skip
Func-
tion
Description
Operation
IC
(6 bits)
B
(4 bits)
C
(4 bits)
SHRC M
Shift memory bits to
right direction with
carry
0
→
(M) b3
→
(M) b2
→
(M) b1
→
(M) b0
→
(CY)
111111
DR
DC
0000
RORC M
Rotate memory bits
to right direction with
carry
(M) b3
→
(M) b2
→
(M) b1
→
(M) b0
→
(CY)
111111
DR
DC
0001
XCH
M
Exchange memory
bits mutually
(M) b3
(M) b0,
(M) b2
(M) b1
111111
DR
DC
0110
DAL ADDR3, r
IF DAL bit
=
0 then
load program in
page 0 to DATA
register. (Note)
DATA
←
[ADDR3
+
(r)] p in page 0
111110
ADDR3 (6 bits)
RN
At P
=
“0” H, the
condition is CPU
waiting (soft wait
mode)
WAIT P
At P
=
“1” H, expect
for clock generator,
all function is waiting
(hard wait mode)
Wait at condition P
111111
P
0100
CKSTP
Clock generator
stop
Stop clock generator
to MODE condition
111111
0101
O
NOOP
No operation
111111
1111
Note: The lower 4 bits of the 10 bits of program memory specified by the DAL instruction (DAL ADDR3r) are used for
indirectly addressing the contents of the general registers.
Note: The DAL instruction execution time is two machine cycles.
Note: The DAL bit and the DAL address register (DA) are located on the I/O map. (See the section on register
ports.)
Note: Executing the DAL instruction with the DAL bit set to 1 invalidates the operand. At this time the DAL address
register (DA) is used for all the addresses to reference. To specify 0, 0 to be operand parts as dummy data at
this time.