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TC9325F
2002-05-14
69
6. Serial Interface 3/4 Control Port, Data Port
Note: When the P5-2 pin is set as a serial data output (SO3/SO4 set), be sure to set the P5-2 I/O control bit
(
φ
L24) to 1 (output state). Setting the P5-2 I/O control bit to 0 sets pin P5-2 to input state. When using pin
P5-1 as a serial input (SI3), be sure to set the P5-1 I/O control bit (
φ
L24) to 0 (input). Setting the P5-1 I/O
control bit to 1 sets pin P5-1 as an output and outputs the P5-1 output data (
φ
L34) as-are.
Note: The output data (pin states) are input to the serial interface.
Y1
Y2
Y4
Y8
φ
L12P3
edge
SCK-INV
SCKO
SIO-ON
I/O port 5 and serial interface selection
0: I/O port 5 (P5-1 to P5-3) selected
1: Serial interface functions selected
External/internal clock selection
0: Input external clock (slave)
1: Output internal clock (master)
Clock signal inversion
0: Negative logic output (output clock from H level)
1: Positive logic output (output clock from L level)
Serial data shift operation logic selection
0: Shift input on clock rising edge, output on rising edge
1: Shift input on clock falling edge, output on falling edge
Y1
Y2
Y4
Y8
φ
L13P3
STA
SI3S
8 bit
Nch
SIO output format selection
(SCK3/SCK4, SO3/SO4 output)
0: CMOS output
1: N-channel open drain output
Selecting the number of serial
data bits
SO3/SO4 pin input/output selection
Starting serial operation and transferring from a serial output data port to a shift
register
0: 4 bits
1: 8 bits
0: Don
’
t care
1: Sets serial output data in the shift register and start serial operation.
Note: The bit is updated under the following conditions.
MOD
SIS
SO3/SO4 Pin
SI3/SI4 Pin
0
Serial output
Serial input
0
1
Serial input
P5-1
input/output
0
Serial output
1
1
Serial input
P5-1
input/output
egde
SCKINV
SI3S Updating
0
1
After STA
=
1 set, updates on serial clock falling edge.
1
0
After STA
=
1 set, updates on serial clock rising edge.
0
0
1
1
Updates when STA
=
1 set.