
SLES208B – JUNE 2009 – REVISED MARCH 2011
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3.2
Terminal Descriptions
TERMINAL
INPUT/
PULLUP/
DESCRIPTION
OUTPUT(1)
PULLDOWN(2)
NAME
NO.
AIN1LM
13
Analog input
Pull to VMID(3)
Analog input, channel 1, left, – input
AIN1LP
12
Analog input
Analog input, channel 1, left, + input
AIN1RM
15
Analog input
Pull to VMID(3)
Analog input, channel 1, right, – input
AIN1RP
14
Analog input
Analog input, channel 1, right, + input
AIN2LM
17
Analog input
Pull to VMID(3)
Analog input, channel 2, left, – input
AIN2LP
16
Analog input
Analog input, channel 2, left, + input
AIN2RM
19
Analog input
Pull to VMID(3)
Analog input, channel 2, right, – input
AIN2RP
18
Analog input
Analog input, channel 2, right, + input
AOUTLM
33
Analog output
Analog output, channel 1, left, – output
AOUTLP
34
Analog output
Analog output, channel 1, left, + output
AOUTRM
35
Analog output
Analog output, channel 1, right, – output
AOUTRP
36
Analog output
Analog output, channel 1, right, + output
3.3-V analog power supply. This pin must be decoupled according to
AVDD1
24
Power
good design practices.
AVSS1
11
Power
Analog supply ground
3.3-V analog power supply. This pin must be decoupled according to
AVDD2
28
Power
good design practices.
AVSS2
37
Power
Analog supply ground
3.3-V analog power supply. This pin must be decoupled according to
AVDD3
40
Power
good design practices.
AVSS3
38
Power
Analog supply ground
CS0
6
Digital input
I2C Chip select
3.3-V digital power supply. This pin must be decoupled according to
DVDD1
9
Power
good design practices.
DVSS1
8
Power
Digital supply ground
3.3-V digital power supply. This pin must be decoupled according to
DVDD2
45
Power
good design practices.
DVSS2
44
Power
Digital supply ground
3.3-V digital power supply. This pin must be decoupled according to
DVDD3
57
Power
good design practices.
DVSS3
56
Power
Digital supply ground
GPIO1
4
Digital I/O
General-purpose input/output
GPIO2
3
Digital I/O
General-purpose input/output
Slave I2C serial clock input/output. Normally connected to the system
I2C1_SCL
1
Digital I/O
microprocessor.
Slave I2C serial control data interface input/output. Normally connected
I2C1_SDA
2
Digital I/O
to system micro.
I2C2_SCL
64
Digital output
Master I2C serial clock output. Normally connected to EEPROM.
Master I2C serial control data interface input/output. Normally
I2C2_SDA
63
Digital I/O
connected to EEPROM.
LRCLK_IN
58
Digital input
Pulldown
Serial data input left/right clock for I2S interface
LRCLK_OUT
51
Digital output
Serial data output left/right clock for I2S interface
MCLK input is used in slave mode. MCLK_IN must be locked to
MCLK_IN
43
Digital input
Pulldown
LRCLK_IN, and the frequency is 512Fs (24.576 MHz for 48-kHz Fs).
MCLK_OUT1
48
Digital output
12.288-MHz clock output. This output is valid even when reset is LOW.
(1)
I = input; O = output
(2)
All pullups are 20-
μA weak pullups, and all pulldowns are 20-μA weak pulldowns. The pullups and pulldowns are included to ensure
proper input logic levels if the terminals are left unconnected (pullups
→ logic 1 input; pulldowns → logic 0 input). Devices that drive
inputs with pullups must be able to sink 20
μA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be
able to source 20
μA while maintaining a logic-1 drive level.
(3)
Pull to VMID when analog input is in single-ended mode.
8
Physical Characteristics
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