參數(shù)資料
型號(hào)： TAS3202PAGR
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù)： 56/66頁(yè)
文件大?。?/td> 817K
代理商： TAS3202PAGR
SLES208B – JUNE 2009 – REVISED MARCH 2011
www.ti.com
I2S clock slave operation:
MCLK_IN (512Fs), SCLK_IN (64Fs), and LRCLK_IN (Fs) are supplied externally. Clock generation is
similar to the master mode with the exception of the ADC and the DAC blocks. MCLK_IN signal is
divided down and sent directly to the ADC and the DAC blocks. Therefore, audio performance
depends on the MCLK_IN signal.
DSP, MCU, and I2C clocks are still derived from external crystal oscillator.
MCLK_OUT, SCLK_OUT, and LRCLK_OUT are passed through from clock inputs (MCLK_IN,
SCLK_IN, and LRCLK_IN).
Internal analog clocks for ADC and DACs are derived from external MCLK_IN input, so analog
performance depends on MCLK_IN quality (i.e., jitter, phase noise, etc.). Degradation in analog
performance is to be expected.
Sample rate change/clock change
–
Sample rate change on the fly should be handled by the customer system controller. The TAS3202
device does not include any internal clock error or click/pop detection/management.
–
Sample rate dependent DAP filter coefficients must be uploaded by customer system controller on
changing sample rate.
In I2S clock slave mode, all incoming serial audio data must be synchronous to an incoming LRCLK_IN of
44.1 kHz or 48 kHz.
2.6
I
2C Control Interface
The TAS3202 has an I2C slave-only interface (SDA1 and SCL1) for receiving commands and providing
status to the system controller, and a separate master I2C interface (SDA2 and SCL2) to download
programs and data from external memory, such as an EEPROM. See Section 6 for more information. I2C
interface is not 5-V tolerant.
2.7
8051 Microcontroller
The 8051 microcontroller receives and distributes I2C write data. It retrieves and outputs data as
requested from the I2C bus controller. It performs most processing tasks requiring multi-frame processing
cycles. The microprocessor has its own data RAM for storing intermediate values and queuing I2C
commands, a fixed boot program ROM, and a programmable RAM. The microprocessor's boot program
cannot be altered. The microcontroller has specialized hardware for an I2C master and slave interface
operation, volume updates, and a programmable interval-timer interrupt.
2.8
Audio Digital Signal Processor (DSP) Core
The audio DSP core arithmetic unit is a fixed-point computational engine consisting of an arithmetic unit
and data and coefficient memory blocks. The audio processing structure, which can include mixers,
multiplexers, volume, bass and treble, equalizers, dynamic range compression, or third-party algorithms, is
running in the DAP. The 8051 microcontroller has access to digital audio processor (DAP) resources such
as coefficient RAM and is able to support the DAP with certain tasks; for example, a volume ramp. The
primary blocks of the audio DSP core are:
48-bit data path with 76-bit accumulator
DSP controller
Memory interface
Coefficient RAM (1K×28)
Data RAM – 24-bit upper memory (1K×24), 48-bit lower memory (768×48)
Program RAM (3K×55)
6
Functional Description
Copyright 2009–2011, Texas Instruments Incorporated
Product Folder Link(s): TAS3202
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TAS3204EVM-LC 制造商:Texas Instruments 功能描述:TAS3204EVM EVALUATION MODULE - Boxed Product (Development Kits)
TAS3204PAG 功能描述:音頻 DSP Hi Perf Dual Core DSP/MCU Aud Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
TAS3204PAGR 功能描述:音頻 DSP Hi Perf Dual Core DSP/MCU Aud Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
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