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SLES208B – JUNE 2009 – REVISED MARCH 2011
1
Introduction
.............................................. 1 7.2
DAP Data Word Structure
..........................
341.1
Features
..............................................
18
Electrical Specifications
............................. 36 1.2
Applications
..........................................
18.1
Absolute Maximum Ratings
........................
361.3
Description
...........................................
18.2
Package Dissipation Ratings
.......................
361.4
Ordering Information
.................................
28.3
Recommended Operating Conditions
2
Functional Description
................................. 4 8.4
Electrical Characteristics
...........................
372.1
Analog Input/Mux/Stereo ADC
.......................
48.5
Audio Specifications
................................
382.2
Stereo DAC
..........................................
48.6
Timing Characteristics
..............................
402.3
Analog Reference System
...........................
48.7
Master Clock
........................................
402.4
Power Supply
........................................
48.8
Serial Audio Port, Slave Mode
2.5
Clocks, Digital Phase-Locked Loop (PLL), and
8.9
Serial Audio Port, Master Mode (TAS3202)
Serial Data Interface
.................................
58.10
Pin-Related Characteristics of the SDA and SCL I/O
2.6
I2C Control Interface
.................................
6Stages for F/S-Mode I2C-Bus Devices
8.11
Bus-Related Characteristics of the SDA and SCL
2.7
8051 Microcontroller
.................................
6I/O Stages for F/S-Mode I2C-Bus Devices
2.8
Audio Digital Signal Processor (DSP) Core
8.12
Reset Timing
.......................................
453
Physical Characteristics
............................... 7 9
I
2C Register Map
....................................... 46 3.1
Terminal Assignments
...............................
79.1
Clock Control Register (0x00)
......................
473.2
Terminal Descriptions
................................
89.2
Status Register (0x02)
..............................
483.3
Reset (RESET) Power-Up Sequence
9.3
I2C Memory Load Control and Memory Load Data
3.4
Voltage Regulator Enable (VREG_EN)
Registers (0x04 and 0x05)
.........................
493.5
Power-On Reset (RESET)
..........................
109.4
Memory Access Registers (0x06 and 0x07)
3.6
Power Down (PDN)
.................................
119.5
Device Version (0x08)
..............................
513.7
I2C Chip Select (CS0)
..............................
119.6
Analog Power Down Control (0x10 and 0x11)
3.8
Programmable General-Purpose I/O (GPIO)
9.7
Analog Input Control (0x12)
........................
523.9
Input and Output Serial Audio Ports
9.8
ADC Dynamic Element Matching (0x13)
4
Algorithm and Software Development Tools for
9.9
ADC Current Control Select (0x17, 0x18)
TAS3202
................................................. 17 9.10
DAC Control (0x1A, 0x1B, 0x1D)
5
Clock Controls
......................................... 18 9.11
ADC and DAC Reset (0x1E)
.......................
576
Microprocessor Controller
.......................... 20 6.1
8051 Microprocessor Addressing Mode
9.12
ADC Input Gain Control (0x1F)
6.2
General I2C Operations
.............................
219.13
MCLK_OUT Divider (0x21 and 0x22)
6.3
I2C Slave-Mode Operation
.........................
239.14
Digital Cross Bar (0x30 to 0x3F)
6.4
I2C Master-Mode Device Initialization
10
Application Information
.............................. 61 7
Digital Audio Processor (DAP) Arithmetic Unit
10.1
Schematics
.........................................
61............................................................. 32 10.2
Recommended Oscillator Circuit
7.1
DAP Instructions Set
...............................
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